Abstract: There is provided a vibration test device capable of accurately performing self-diagnosis related to the state of the vibration test device, including a failure determination, a failure prediction, and a performance limit determination of the vibration test device.

Abstract: A control method for a display device includes: determining whether an illuminance in an environment where a display device having a light source is installed belongs to a first range or a second range; when the illuminance in the environment belongs to the first range, adjusting a luminance of the light source by referring to first luminance information designating the luminance corresponding to when the illuminance in the environment belongs to the first range; when the illuminance in the environment belongs to the second range, adjusting the luminance by referring to second luminance information designating the luminance corresponding to when the illuminance in the environment belongs to the second range; when a first operation of changing the luminance when the illuminance belongs to the first range is accepted from a user, updating the first luminance information to an updated first luminance information in response to the first operation; updating the second luminance information, based on the updated f

Abstract: There is provided a vibration test support network system that connects a plurality of vibration test devices via a network and supports maintenance of vibration test devices and stabilization of accuracy of the vibration test through analysis of self-diagnosis information by the vibration test devices. A vibration test support network system 300 includes a plurality of vibration test devices 200, a network 210 connecting the plurality of vibration test devices 200, and an analysis device 220 connected to the network 210 and configured to transmit and receive information to and from the plurality of vibration test devices 200 via the network 210.

Abstract: There is provided a vibration test support network system that connects a plurality of vibration test devices via a network and supports maintenance of vibration test devices and stabilization of accuracy of the vibration test through analysis of self-diagnosis information by the vibration test devices. A vibration test support network system 300 includes a plurality of vibration test devices 200, a network 210 connecting the plurality of vibration test devices 200, and an analysis device 220 connected to the network 210 and configured to transmit and receive information to and from the plurality of vibration test devices 200 via the network 210.

Abstract: According to one embodiment, a memory device includes: a first conductive layer; a first conductive film extending in a first direction above the first conductive layer; a first semiconductor film extending in the first direction between the first conductive layer and the first conductive film and intersecting the first conductive layer; a second semiconductor film that is in contact with the first semiconductor film, extends in the first direction between the first conductive layer and the first conductive film, and faces the first conductive film; a first insulating film provided between the first conductive layer and the first semiconductor film; and a second insulating film provided between the first conductive film and each of the first semiconductor film and the second semiconductor film.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.

Abstract: A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.

Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

Abstract: A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.

Abstract: According to one embodiment, a memory device includes a plurality of first conductors stacked along a first direction; a second, third, and fourth conductor stacked in a same layer above the first conductors; a plurality of fifth conductors stacked along the first direction; a sixth conductor stacked above the fifth conductors; a first semiconductor extending along the first direction between the second conductor and the sixth conductor; a second semiconductor extending along the first direction between the third conductor and the sixth conductor; and a third semiconductor extending along the first direction between the fourth conductor and the sixth conductor.

Abstract: A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.

Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.

Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.