Patents by Inventor Yasuhiro Usui
Yasuhiro Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10408756Abstract: For an analysis method, a first specimen and a second specimen are prepared, in which different phthalate esters, for example DEHP and DINP, adhere in different states to a pair of predetermined base films, such as PVC, on metal plates. A metal reflection IR spectrum (P) and a metal reflection IR spectrum (Q) are acquired by radiating electromagnetic waves on the prepared first specimen and the second specimen respectively. Significantly different spectra are obtained for different phthalate esters, and the types of phthalate esters are identified by using such spectra.Type: GrantFiled: January 27, 2017Date of Patent: September 10, 2019Assignee: FUJITSU LIMITEDInventors: Michiko Noguchi, Mitsuo Ozaki, Yasuhiro Usui
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Publication number: 20170138850Abstract: For an analysis method, a first specimen and a second specimen are prepared, in which different phthalate esters, for example DEHP and DINP, adhere in different states to a pair of predetermined base films, such as PVC, on metal plates. A metal reflection IR spectrum (P) and a metal reflection IR spectrum (Q) are acquired by radiating electromagnetic waves on the prepared first specimen and the second specimen respectively. Significantly different spectra are obtained for different phthalate esters, and the types of phthalate esters are identified by using such spectra.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Applicant: FUJITSU LIMITEDInventors: Michiko NOGUCHI, Mitsuo OZAKI, Yasuhiro Usui
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Patent number: 7291901Abstract: A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12, a thin film substrate (a second substrate) 13 is laminated on the first substrate 12, the opening 11 is covered with the thin film substrate 13. Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15, an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13, and the capacitor 14 is connected to the LSI 16.Type: GrantFiled: March 19, 2004Date of Patent: November 6, 2007Assignee: Fujitsu LimitedInventors: Masateru Koide, Misao Umematsu, Takashi Kanda, Yasuhiro Usui, Kenji Fukuzono
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Patent number: 7268002Abstract: A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12, a thin film substrate (a second substrate) 13 is laminated on the first substrate 12, the opening 11 is covered with the thin film substrate 13. Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15, an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13, and the capacitor 14 is connected to the LSI 16.Type: GrantFiled: November 3, 2005Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventors: Masateru Koide, Misao Umematsu, Takashi Kanda, Yasuhiro Usui, Kenji Fukuzono
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Publication number: 20060215810Abstract: The present invention has been made to obtain a fluorescent X-ray analyzer and the like capable of easily performing analysis of a sample including materials in the form of a multiple layer in the depth direction of the sample at low cost without a need of a skilled technique and time. A fluorescent X-ray analysis method according to the present invention that performs analysis of materials in a sample including different materials in the form of a multiple layer analyzes the materials by irradiating the sample with an X-ray to detect an fluorescent X-ray; estimates a processing amount for the sample based on a result of the analysis; and applies processing to the sample based on the processing amount estimated in the processing amount estimation step.Type: ApplicationFiled: July 29, 2005Publication date: September 28, 2006Applicant: FUJITSU LIMITEDInventor: Yasuhiro Usui
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Publication number: 20060063303Abstract: A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12, a thin film substrate (a second substrate) 13 is laminated on the first substrate 12, the opening 11 is covered with the thin film substrate 13. Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15, an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13, and the capacitor 14 is connected to the LSI 16.Type: ApplicationFiled: November 3, 2005Publication date: March 23, 2006Applicant: FUJITSU LIMITEDInventors: Masateru Koide, Misao Umematsu, Takashi Kanda, Yasuhiro Usui, Kenji Fukuzono
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Publication number: 20050110169Abstract: According to a method of making a semiconductor device, a semiconductor chip is bonded to a substrate via bumps by flip-chip bonding. Then, a sealing adhesive composition is loaded between the semiconductor chip and the substrate to provide an adhesive sealing. The sealing adhesive composition, which is capable of hardening in two stages, contains at least a first main resin ingredient, a second main resin ingredient and a hardening agent. Then, the adhesive sealing is heated for primary hardening. Then, the substrate is placed on a mother board with a solder material interposed between the substrate and the mother board. Finally, the adhesive sealing is heated for secondary hardening while the solder material is reflowed for bonding the substrate to the mother board.Type: ApplicationFiled: December 23, 2004Publication date: May 26, 2005Applicant: FUJITSU LIMITEDInventors: Tomohisa Yagi, Nobuhiro Imaizumi, Yasuhiro Usui, Kenji Fukuzono
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Patent number: 6869822Abstract: According to a method of making a semiconductor device, a semiconductor chip is bonded to a substrate via bumps by flip-chip bonding. Then, a sealing adhesive composition is loaded between the semiconductor chip and the substrate to provide an adhesive sealing. The sealing adhesive composition, which is capable of hardening in two stages, contains at least a first main resin ingredient, a second main resin ingredient and a hardening agent. Then, the adhesive sealing is heated for primary hardening. Then, the substrate is placed on a mother board with a solder material interposed between the substrate and the mother board. Finally, the adhesive sealing is heated for secondary hardening while the solder material is reflowed for bonding the substrate to the mother board.Type: GrantFiled: March 26, 2002Date of Patent: March 22, 2005Assignee: Fujitsu LimitedInventors: Tomohisa Yagi, Nobuhiro Imaizumi, Yasuhiro Usui, Kenji Fukuzono
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Publication number: 20040183193Abstract: A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12, a thin film substrate (a second substrate) 13 is laminated on the first substrate 12, the opening 11 is covered with the thin film substrate 13. Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15, an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13, and the capacitor 14 is connected to the LSI 16.Type: ApplicationFiled: March 19, 2004Publication date: September 23, 2004Applicant: FUJITSU LIMITEDInventors: Masateru Koide, Misao Umematsu, Takashi Kanda, Yasuhiro Usui, Kenji Fukuzono
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Publication number: 20030049888Abstract: According to a method of making a semiconductor device, a semiconductor chip is bonded to a substrate via bumps by flip-chip bonding. Then, a sealing adhesive composition is loaded between the semiconductor chip and the substrate to provide an adhesive sealing. The sealing adhesive composition, which is capable of hardening in two stages, contains at least a first main resin ingredient, a second main resin ingredient and a hardening agent. Then, the adhesive sealing is heated for primary hardening. Then, the substrate is placed on a mother board with a solder material interposed between the substrate and the mother board. Finally, the adhesive sealing is heated for secondary hardening while the solder material is reflowed for bonding the substrate to the mother board.Type: ApplicationFiled: March 26, 2002Publication date: March 13, 2003Applicant: Fujitsu LimitedInventors: Tomohisa Yagi, Nobuhiro Imaizumi, Yasuhiro Usui, Kenji Fukuzono
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Patent number: 6057168Abstract: A method for forming bumps including the steps of forming bumps on a dummy wafer. The dummy wafer is diced into dummy chips and the bumps formed on the dummy chips are inspected. Thus only good bumps are transferred to a real chip on which circuit patterns are formed.Type: GrantFiled: January 27, 1999Date of Patent: May 2, 2000Assignee: Fujitsu LimitedInventors: Kiyotaka Seyama, Hideki Ota, Yasuhiro Usui, Kazuaki Satoh