Patents by Inventor Yasuhiro Yoshiura
Yasuhiro Yoshiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299191Abstract: According to the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, in which a cell region, a ballast resistor region, and a termination region surrounding the ballast resistor region are defined, a first insulating film arranged on a front surface of the semiconductor substrate, having a first opening in the cell region, and having at least one second opening in the ballast resistor region, a second insulating film filled in the at least one second opening, a first impurity layer of a second conductivity type arranged on the front surface of the semiconductor substrate below the first opening, and a second impurity layer of the second conductivity type arranged on the front surface of the semiconductor substrate below the at least one second opening, a conductive film arranged from the front surface of the first opening of the semiconductor substrate to the termination region.Type: ApplicationFiled: December 15, 2022Publication date: September 21, 2023Applicant: Mitsubishi Electric CorporationInventors: Yasuhiro YOSHIURA, Eiko OTSUKI, Hayato OKAMOTO
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Patent number: 10811511Abstract: It is an object of the present invention to easily perform an electric characteristic test for ensuring quality of a semiconductor device on an electrode pattern defect or deficiency. A method of manufacturing a semiconductor device according to the present invention performs, a first etching having a higher selected ratio with respect to a semiconductor material of a first semiconductor layer than a material of a first electrode film over the first electrode film, and removes a region in the first semiconductor layer below a pattern defective part or a deficiency part of the first electrode film at least partially to form an electrode film in the pattern defective part or the deficiency part of the first electrode film.Type: GrantFiled: August 25, 2016Date of Patent: October 20, 2020Assignee: Mitsubishi Electric CorporationInventors: Takao Kachi, Yasuhiro Yoshiura
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Publication number: 20190319109Abstract: It is an object of the present invention to easily perform an electric characteristic test for ensuring quality of a semiconductor device on an electrode pattern defect or deficiency. A method of manufacturing a semiconductor device according to the present invention performs, a first etching having a higher selected ratio with respect to a semiconductor material of a first semiconductor layer than a material of a first electrode film over the first electrode film, and removes a region in the first semiconductor layer below a pattern defective part or a deficiency part of the first electrode film at least partially to form an electrode film in the pattern defective part or the deficiency part of the first electrode film.Type: ApplicationFiled: August 25, 2016Publication date: October 17, 2019Applicant: Mitsubishi Electric CorporationInventors: Takao KACHI, Yasuhiro YOSHIURA
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Patent number: 10340133Abstract: A silicon oxide film having at least one opening portion is formed, on a silicon substrate. A structural member formed of a material less prone to be etched by hydrofluoric acid than a silicon oxide film is formed, wherein the structural member is provided on the silicon oxide film and reaches the silicon substrate in the opening portion. Wet etching using hydrofluoric acid is performed, on the silicon substrate on which the silicon oxide film and the structural member are provided. The interface between the silicon oxide film and the structural member is exposed to hydrofluoric acid, in performing the wet etching.Type: GrantFiled: July 15, 2015Date of Patent: July 2, 2019Assignee: Mitsubishi Electric CorporationInventors: Takao Kachi, Yasuhiro Yoshiura
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Publication number: 20180190508Abstract: A silicon oxide film having at least one opening portion is formed, on a silicon substrate. A structural member formed of a material less prone to be etched by hydrofluoric acid than a silicon oxide film is formed, wherein the structural member is provided on the silicon oxide film and reaches the silicon substrate in the opening portion. Wet etching using hydrofluoric acid is performed, on the silicon substrate on which the silicon oxide film and the structural member are provided. The interface between the silicon oxide film and the structural member is exposed to hydrofluoric acid, in performing the wet etching.Type: ApplicationFiled: July 15, 2015Publication date: July 5, 2018Applicant: Mitsubishi Electric CorporationInventors: Takao KACHI, Yasuhiro YOSHIURA
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Patent number: 9755037Abstract: According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.Type: GrantFiled: December 30, 2014Date of Patent: September 5, 2017Assignee: Mitsubishi Electric CorporationInventors: Takao Kachi, Masayoshi Tarutani, Yasuhiro Yoshiura
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Patent number: 9704946Abstract: A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side, an n-type ultrahigh-concentration impurity layer and an n-type high-concentration impurity layer to serve as a cathode are formed. In a guard-ring opposed region located in the cathode and opposite to the guard ring, a cathode-side p-type diffusion region is formed. Accordingly, concentration of the electric current on an outer peripheral end portion of the anode is suppressed.Type: GrantFiled: May 6, 2015Date of Patent: July 11, 2017Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuhiro Yoshiura, Masanori Inoue
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Patent number: 9455355Abstract: An n?-type semiconductor substrate (1) includes an active region and a terminal region disposed outside the active region. A p+-type anode layer (2) is formed in a portion of an upper surface of the n?-type semiconductor substrate (1) in the active region. A plurality of p+-type guard ring layers (3) are formed in a portion of the upper surface of the n?-type semiconductor substrate (1) in the terminal region. An n+-type cathode layer (5) is formed in a lower surface of the n?-type semiconductor substrate (1). An anode electrode (6) is connected to the p+-type anode layer (2). A metallic cathode electrode (7) is connected to the n+-type cathode layer (5). A recess (8) is formed by trenching the n+-type cathode layer (5) in the terminal region. The cathode electrode (7) is also formed in the recess (8).Type: GrantFiled: July 8, 2013Date of Patent: September 27, 2016Assignee: Mitsubishi Electric CorporationInventors: Eiko Otsuki, Koji Sadamatsu, Yasuhiro Yoshiura
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Patent number: 9401314Abstract: A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having a main current flowing therethrough, the termination structure surrounding the cell structure, the method includes a first test step of testing dielectric strength of the semiconductor device, a charge removal step of, after the first test step, removing charge from a top surface layer of the termination structure, the top surface layer being located on the substrate and formed of an insulating film or a semi-insulating film, and a second test step of, after the charge removal step, testing dielectric strength of the semiconductor device.Type: GrantFiled: April 1, 2014Date of Patent: July 26, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Eiko Otsuki, Yasuhiro Yoshiura, Koji Sadamatsu
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Publication number: 20160087110Abstract: An n?-type semiconductor substrate (1) includes an active region and a terminal region disposed outside the active region. A p+-type anode layer (2) is formed in a portion of an upper surface of the n?-type semiconductor substrate (1) in the active region. A plurality of p+-type guard ring layers (3) are formed in a portion of the upper surface of the n?-type semiconductor substrate (1) in the terminal region. An n+-type cathode layer (5) is formed in a lower surface of the n?-type semiconductor substrate (1). An anode electrode (6) is connected to the p+-type anode layer (2). A metallic cathode electrode (7) is connected to the n+-type cathode layer (5). A recess (8) is formed by trenching the n+-type cathode layer (5) in the terminal region. The cathode electrode (7) is also formed in the recess (8).Type: ApplicationFiled: July 8, 2013Publication date: March 24, 2016Applicant: MIitsubishi Electric CorporationInventors: Eiko OTSUKI, Koji SADAMATSU, Yasuhiro YOSHIURA
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Patent number: 9257541Abstract: A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p+-type diffusion region, a p?-type region, and an anode electrode. The p?-type region is formed as a region of relatively high electrical resistance sandwiched between the p+-type diffusion regions.Type: GrantFiled: July 24, 2013Date of Patent: February 9, 2016Assignee: Mitsubishi Electric CorporationInventors: Eiko Otsuki, Koji Sadamatsu, Yasuhiro Yoshiura
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Publication number: 20150294871Abstract: According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.Type: ApplicationFiled: December 30, 2014Publication date: October 15, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takao KACHI, Masayoshi TARUTANI, Yasuhiro YOSHIURA
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Patent number: 9159563Abstract: A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps.Type: GrantFiled: September 26, 2012Date of Patent: October 13, 2015Assignee: Mitsubishi Electric CorporationInventors: Tomohide Terashima, Yasuhiro Yoshiura, Eiko Otsuki
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Publication number: 20150236088Abstract: A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side, an n-type ultrahigh-concentration impurity layer and an n-type high-concentration impurity layer to serve as a cathode are formed. In a guard-ring opposed region located in the cathode and opposite to the guard ring, a cathode-side p-type diffusion region is formed. Accordingly, concentration of the electric current on an outer peripheral end portion of the anode is suppressed.Type: ApplicationFiled: May 6, 2015Publication date: August 20, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuhiro YOSHIURA, Masanori INOUE
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Publication number: 20150228488Abstract: A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps.Type: ApplicationFiled: September 26, 2012Publication date: August 13, 2015Applicant: Mitsubishi Electric CorporationInventors: Tomohide Terashima, Yasuhiro Yoshiura, Eiko Otsuki
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Publication number: 20140363906Abstract: A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having a main current flowing therethrough, the termination structure surrounding the cell structure, the method includes a first test step of testing dielectric strength of the semiconductor device, a charge removal step of, after the first test step, removing charge from a top surface layer of the termination structure, the top surface layer being located on the substrate and formed of an insulating film or a semi-insulating film, and a second test step of, after the charge removal step, testing dielectric strength of the semiconductor device.Type: ApplicationFiled: April 1, 2014Publication date: December 11, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Eiko OTSUKI, Yasuhiro YOSHIURA, Koji SADAMATSU
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Publication number: 20140232004Abstract: The present invention includes a semiconductor substrate and a back electrode (a back multilayer electrode in the preferred embodiment) provided on a back surface of the semiconductor substrate. A rough source pattern is formed in a peripheral edge portion of the back surface of the semiconductor substrate which faces the back multilayer electrode.Type: ApplicationFiled: October 24, 2013Publication date: August 21, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuhiro YOSHIURA, Masayoshi TARUTANI, Eiko OTSUKI
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Patent number: 8698250Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer.Type: GrantFiled: June 18, 2012Date of Patent: April 15, 2014Assignee: Mitsubishi Electric CorporationInventors: Takao Kachi, Yasuhiro Yoshiura, Fumihito Masuoka
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Publication number: 20140091359Abstract: A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p+-type diffusion region, a p?-type region, and an anode electrode. The p?-type region is formed as a region of relatively high electrical resistance sandwiched between the p+-type diffusion regions.Type: ApplicationFiled: July 24, 2013Publication date: April 3, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Eiko OTSUKI, Koji SADAMATSU, Yasuhiro YOSHIURA
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Publication number: 20130093065Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer.Type: ApplicationFiled: June 18, 2012Publication date: April 18, 2013Applicant: Mitsubishi Electric CorporationInventors: Takao KACHI, Yasuhiro YOSHIURA, Fumihito MASUOKA