Abstract: A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area.

Abstract: A cache memory is equipped with a cache memory area, a conversion information storing unit, and a conversion circuit. In the cache memory area, a plurality of sets are divided into a plurality of sectors. The conversion information storing unit stores, for each of the plurality of sectors, conversion information for converting a relative set index in a sector into a set index in the cache memory area. The conversion circuit converts the relative set index in the sector indicated by the sector identification information to a set index that indicates a set accessed by the processor in the cache memory area, using sector identification information that identifies an access-target sector and the conversion information stored in the conversion information storing unit.

Abstract: A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area.