Patents by Inventor Yasuhisa Marumo

Yasuhisa Marumo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854638
    Abstract: A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 26, 2023
    Assignee: MEGACHIPS CORPORATION
    Inventors: Shunsuke Nakai, Atsufumi Kawamura, Yasuhisa Marumo, Handa Chen
  • Publication number: 20220254426
    Abstract: A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 11, 2022
    Applicant: MegaChips Corporation
    Inventors: Shunsuke NAKAI, Atsufumi KAWAMURA, Yasuhisa MARUMO, Handa CHEN
  • Patent number: 8015370
    Abstract: A memory control method includes writing converted data which is produced by carrying out a code conversion on original data into a memory. An amount of 1s in the converted data is less than an amount of 1s in the original data. Further, the memory control method includes outputting reproduced data which is provided by carrying out an inverse transformation of the code conversion on the converted data which is read out from the memory, to a host system for processing the original data.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: September 6, 2011
    Assignee: MegaChips Corporation
    Inventors: Tetsuo Furuichi, Yasuhisa Marumo
  • Publication number: 20080201538
    Abstract: Error-tolerant code conversion is carried out on original data including a large amount of binary data which is apt to be unintentionally rewritten, to produce converted data including a smaller amount of binary data which is apt to be unintentionally rewritten, and the converted data is written into a memory. While a host system is processing the original data, the memory reads out the converted data and the code inverse transformation part carries out inverse transformation of error-tolerant code conversion on the converted data, to output reproduced data which is identical to the original data, to the host system. As a result, it is possible to avoid or suppress the possibility that data is unintentionally rewritten due to repeated readout of the same data.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 21, 2008
    Applicant: MegaChips Corporation
    Inventors: Tetsuo Furuichi, Yasuhisa Marumo