Abstract: A constant voltage generating circuit includes a first power supply line coupled to an external power supply line, at least one second power supply line having a voltage different from that of the first power supply line, a level shift circuit having at least one transistor coupled between the first power supply line and the second power supply line, a resistor having one end connected to one of the first and second power supply lines and other end coupled to a base of a transistor provided at a final stage of the level shift circuit, and a current control circuit operatively connected between the other end of the resistor and another of the first and second power supply lines. The current control circuit suitably controls current flowing in the resistor. As a result, it is possible to continually feed a constant voltage irrespective of a fluctuation in temperature, power supply voltage, or the like.

Abstract: A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and circuitry for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part located in one of the blocks is reversed to that of the writing part located in another block adjacent thereto, whereby the two facing bit lines of different blocks assume opposite logic levels when the same data logic is written into all the memory cells.

Abstract: This invention relates to a semiconductor memory having flip-flops which hold the address input in order to absorb skew thereof within the same chip. The flip-flops are connected to be of the master-slave type and an address decoder is provided between the master flip-flops and the slave flip-flops. A part of the time required for latching the address signal into the master flip-flops and a part of the time required for decoder operation are overlapped, and thereby a high operation rate can be realized. Parts of the circuits forming the flip-flop circuits are used in common to the address input buffer and also in common to the word line driver circuits.

Abstract: A semiconductor memory device in which a bipolar memory cell includes two cross-coupled transistors. The collector load is a Schottky barrier diode. A capacitor is formed to be connected to the Schottky barrier diode. The capacitor is formed by a junction between a P.sup.+ -type diffusion region and an N.sup.+ -type buried layer functioning as a collector of the transistor. The P.sup.+ -type diffusion region is formed in the periphery of the Schottky barrier diode and between a metal layer connected to a word line and the N.sup.+ -type buried layer. By the capacitor, the stability of the memory holding state is improved without deteriorating the operating speed of the memory cell.

Abstract: A semiconductor memory device includes at least, a memory cell including a first Schottky diode therein, a word line, a bit line, a first constant-current circuit for the word line, a second constant-current circuit for the bit line, and a bias circuit for biasing the first and second constant-current circuits. The bias circuit contains therein a second Schottky barrier diode. A forward voltage V.sub.F of the second Schottky barrier diode is substantially the same as that of the first Schottky barrier diode.

Abstract: A semiconductor memory includes memory cells each respectively provided with a flip-flop circuit in which a pair of transistors is included, the flip-flop circuit being connected to a pair of bit lines and to a pair of word lines. The semiconductor memory further includes a pair of switching transistors connected to the pair of bit lines. One of the pair of switching transistors is turned ON while the other is turned OFF when they receive high and low potentials according to write data at the time of a write operation so as to flow write current from a memory cell to a voltage source via one of the pair of bit lines and one of the pair of switching transistors.

Abstract: A semiconductor memory device comprising a circuit which effects the flow of a discharge current to a selected word line, wherein a circuit for detecting change of a decoder input is provided, and thereby the discharge current flows temporarily only when the selected word line shifts to the non-selected condition.

Abstract: A static semiconductor memory device comprises memory cells arranged in a matrix having columns and rows, and bit selection circuits provided in the respective columns. Each of the bit selection circuits is adapted to receive a column selection signal, having a high reference potential, when the corresponding column is selected for supplying a current to the selected column. A discharge path is provided in each bit selection circuit so that the potential of the column selection signal is rapidly lowered when the column is switched from a selected state to a nonselected state, whereby the power consumption is lowered and high speed operation is achieved.