Patents by Inventor Yasuhisa Tamura

Yasuhisa Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for alleviating fatigue
    Patent number: 11458178
    Abstract: The present invention provides a novel IL-1? and/or IL-6 expression inhibitor and use thereof. The IL-1? and/or IL-6 expression inhibitor in accordance with an aspect of the present invention contains a component derived from alcoholic fermentation lees.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 4, 2022
    Assignees: RIKEN, OZEKI CORPORATION
    Inventors: Masanori Yamato, Yosky Kataoka, Yasuhisa Tamura, Satoshi Kume, Toshitaka Minetoki, Kazuhisa Hizume, Satoshi Okazaki, Miyo Hirata, Shinya Okuda, Takayuki Bogaki
  • INHIBITOR OF IL-1BETA AND/OR IL-6 EXPRESSION, AND USE OF SAID INHIBITOR
    Publication number: 20210106634
    Abstract: The present invention provides a novel IL-1? and/or IL-6 expression inhibitor and use thereof. The IL-1? and/or IL-6 expression inhibitor in accordance with an aspect of the present invention contains a component derived from alcoholic fermentation lees.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 15, 2021
    Inventors: Masanori YAMATO, Yosky KATAOKA, Yasuhisa TAMURA, Satoshi KUME, Toshitaka MINETOKI, Kazuhisa HIZUME, Satoshi OKAZAKI, Miyo HIRATA, Shinya OKUDA, Takayuki BOGAKI
  • Buffer storage control system
    Patent number: 5377341
    Abstract: In buffer storage equipment, storage control is carried out by a pipeline having two stages including a stage for executing out-of-order processing for processing a succeeding request with priority and a stage for not executing out-of-order processing. By this storage control, a request processing order is guaranteed at the stage for not executing out-of-order processing and a request is caused to wait at the stage for executing out-of-order processing.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: December 27, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Kaneko, Toshiyuki Kinoshita, Akio Yamamoto, Yasuhisa Tamura
  • Task scheduling method in a multiprocessor system where task selection is determined by processor identification and evaluation information
    Patent number: 5349656
    Abstract: A task scheduling method for a multiprocessor in a computer system having a main storage unit and a plurality of instruction processors each having a buffer storage unit, the buffer storage unit having a copy of a part of the main storage unit and deleting a part of the copy when reading a main storage unit area not stored in the buffer storage unit.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: September 20, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Kaneko, Toshiyuki Kinoshita, Akio Yamamoto, Yasuhisa Tamura
  • Main memory addressing system
    Patent number: 5333289
    Abstract: In a computer system having a main storage equipment comprising a plurality of storage equipments, the storage area of each storage equipment is divided in fixed units and an interleave mode is set for each of fixed nuts. When configuration of the main storage equipment is to be changed by disconnection or coupling of storage equipments, necessary data are moved and the interleave mode is changed for all data of the above described fixed unit.
    Type: Grant
    Filed: May 21, 1991
    Date of Patent: July 26, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Kaneko, Masaya Watanabe, Toshiyuki Kinoshita, Yasuhisa Tamura, Masaichiro Yoshioka