Patents by Inventor Yasuhito Hyakutake

Yasuhito Hyakutake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof
    Patent number: 6087250
    Abstract: A highly reliable semiconductor device having superior flatness and highly precise pattern is obtained. A first metal interconnection 7a is formed on a semiconductor substrate 1. An interlayer insulating film 8a is provided on semiconductor substrate 1 to cover the first metal interconnection 7a. A second metal interconnection 7b is provided on the interlayer insulating film 8a. The interlayer insulating film 8a includes a first silicon oxide film 107a provided on semiconductor substrate 1 to cover the first metal interconnection 7a, and a second silicon oxide film 108a provided to fill concave portions at the surface of the first silicon oxide film 107a. Height of the interlayer insulating film 8a from the surface of the semiconductor substrate 1 is made uniform entirely over one chip.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: July 11, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuhito Hyakutake
  • Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof
    Patent number: 5763954
    Abstract: A highly reliable semiconductor device having superior flatness and highly precise pattern is obtained. A first metal interconnection 7a is formed on a semiconductor substrate 1. An interlayer insulating film 8a is provided on semiconductor substrate 1 to cover the first metal interconnection 7a. A second metal interconnection 7b is provided on the interlayer insulating film 8a. The interlayer insulating film 8a includes a first silicon oxide film 107a provided on semiconductor substrate 1 to cover the first metal interconnection 7a, and a second silicon oxide film 108a provided to fill concave portions at the surface of the first silicon oxide film 107a. Height of the interlayer insulating film 8a from the surface of the semiconductor substrate 1 is made uniform entirely over one chip.
    Type: Grant
    Filed: April 25, 1996
    Date of Patent: June 9, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuhito Hyakutake