Patents by Inventor Yasuhito Iguchi

Yasuhito Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10481177
    Abstract: A wafer inspection method improving inspection accuracy and operation efficiency. A method for performing electrical inspection by bringing into contact with pads in chips on a wafer. A chuck step S1 for heating the wafer to an inspection temperature; a first position recognition step S2 for recognizing all the positions of the pads; a second position recognition step S3 for re-recognizing, before performing the electrical inspection, the position of the pads recognizing the positional shifts of the pads due to thermal expansion; and a correction step S4 for correcting contact positions with respect to the probes, the contact positions being corrected on the basis of pad positions, which have been re-recognized in the second position recognition step S3 on the basis of the pad positions recognized in the first position recognition step S2, and which have been updated.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 19, 2019
    Assignee: Tokyo Seimitsu Co. LTD.
    Inventors: Yuichi Ozawa, Yasuhito Iguchi, Tetsuo Yoshida, Junzo Koshio
  • Patent number: 9983256
    Abstract: To provide a probing device and a probing method for an electronic device capable of confirming whether or not an electrical inspection has been executed appropriately, with an electrode pad being made in contact with a probe with a predetermined pressure, by utilizing a change in external shapes to be formed on the electrode pad when the probe and the electrode pad are pressed onto each other.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: May 29, 2018
    Assignee: Tokyo Seimitsu Co. LTD
    Inventors: Yuichi Ozawa, Yasuhito Iguchi, Tetsuo Yoshida, Junzo Koshio
  • Publication number: 20170322236
    Abstract: A wafer inspection method whereby inspection accuracy and operation efficiency is improved. A method for performing electrical inspection by bringing, at one time, a plurality of probes into contact with a plurality of pads in chips on a wafer. A chuck step S1 for heating the wafer to an inspection temperature; a first position recognition step S2 for recognizing all the positions of the pads of the chips; a second position recognition step S3 for re-recognizing, before performing the electrical inspection, the position of the pads for the purpose of recognizing the positional shifts of the pads due to thermal expansion when the wafer chuck is heated; and a correction step S4 for correcting contact positions with respect to the probes, the contact positions being corrected on the basis of pad positions, which have been re-recognized in the second position recognition step S3 on the basis of the pad positions recognized in the first position recognition step S2, and which have been updated.
    Type: Application
    Filed: November 26, 2014
    Publication date: November 9, 2017
    Inventors: Yuichi OZAWA, Yasuhito IGUCHI, Tetsuo YOSHIDA, Junzo KOSHIO
  • Patent number: 9664733
    Abstract: A probe device of the present invention measures a position of every chip in a wafer to be inspected to acquire the position as actual measurement data. Then, the probe device calculates a variation amount of an actual measurement position of each chip or a variation amount of a position at which a probe is brought into contact with the each chip of the wafer on the basis of the actual measurement data, and allows a monitor to display a range-of-variation display image that visually displays the variation amount. In the image, a quadrangular area corresponding to the each chip is displayed, and a dot is displayed in each the quadrangular area at a position shifted from a center position thereof in accordance with the variation amount.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: May 30, 2017
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Yuichi Ozawa, Hiroshi Nishimura, Seiichi Ohta, Yasuhito Iguchi, Kunihiko Chiba, Ken Kato
  • Patent number: 9442156
    Abstract: The present invention provides a probe device that includes an alignment utility function. When a user inputs a condition value for a variation amount (variation range) of a contact position at which a probe is in contact with each chip, in a simulation using actual measurement data acquired by measuring a position of each of all chips in one wafer, a range of variation of each chip is calculated by changing a measurement point at which alignment is performed to calculate a setting of optimum measurement points so that the range of variation is equal to or less than the condition value and the number of measurement points is minimum. Then information on the optimum measurement point is provided to the user.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 13, 2016
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Yuichi Ozawa, Hiroshi Nishimura, Seiichi Ohta, Yasuhito Iguchi, Kunihiko Chiba, Ken Kato
  • Publication number: 20150362552
    Abstract: A probe device of the present invention measures a position of every chip in a wafer to be inspected to acquire the position as actual measurement data. Then, the probe device calculates a variation amount of an actual measurement position of each chip or a variation amount of a position at which a probe is brought into contact with the each chip of the wafer on the basis of the actual measurement data, and allows a monitor to display a range-of-variation display image that visually displays the variation amount. In the image, a quadrangular area corresponding to the each chip is displayed, and a dot is displayed in each the quadrangular area at a position shifted from a center position thereof in accordance with the variation amount.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Applicant: TOKYO SEIMITSU CO., LTD.
    Inventors: Yuichi Ozawa, Hiroshi Nishimura, Seiichi Ohta, Yasuhito Iguchi, Kunihiko Chiba, Ken Kato
  • Publication number: 20150362553
    Abstract: The present invention provides a probe device that includes an alignment utility function. When a user inputs a condition value for a variation amount (variation range) of a contact position at which a probe is in contact with each chip, in a simulation using actual measurement data acquired by measuring a position of each of all chips in one wafer, a range of variation of each chip is calculated by changing a measurement point at which alignment is performed to calculate a setting of optimum measurement points so that the range of variation is equal to or less than the condition value and the number of measurement points is minimum. Then information on the optimum measurement point is provided to the user.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Applicant: Tokyo Seimitsu Co., Ltd.
    Inventors: Yuichi Ozawa, Hiroshi Nishimura, Seiichi Ohta, Yasuhito Iguchi, Kunihiko Chiba, Ken Kato
  • Publication number: 20150109625
    Abstract: To provide a probing device and a probing method for an electronic device capable of confirming whether or not an electrical inspection has been executed appropriately, with an electrode pad being made in contact with a probe with a predetermined pressure, by utilizing a change in external shapes to be formed on the electrode pad when the probe and the electrode pad are pressed onto each other.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 23, 2015
    Inventors: Yuichi Ozawa, Yasuhito Iguchi, Tetsuo Yoshida, Junzo Koshio