Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The memory stores first information and second information. The first information includes a permission time with respect to each of a plurality of operation states of the information processing apparatus in an activation state. The permission time is a time allowed for switching a substitute apparatus from a standby state to the activation state. The second information includes an activation time required for activating each of a plurality of modules which operate on the substitute apparatus. The processor identifies one permission time corresponding to a current operation state. The processor determines stop modules such that a total time for activating the stop modules is equal to or less than the one permission time based on the second information. The processor instructs the substitute apparatus in the standby state to stop the stop modules.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The memory stores first information and second information. The first information includes a permission time with respect to each of a plurality of operation states of the information processing apparatus in an activation state. The permission time is a time allowed for switching a substitute apparatus from a standby state to the activation state. The second information includes an activation time required for activating each of a plurality of modules which operate on the substitute apparatus. The processor identifies one permission time corresponding to a current operation state. The processor determines stop modules such that a total time for activating the stop modules is equal to or less than the one permission time based on the second information. The processor instructs the substitute apparatus in the standby state to stop the stop modules.

Abstract: A virtualization controller identifies a node that manages a segment to be accessed, and instructs the node to access the segment. A mirror controller of the node instructed to access the segment writes data in the segment managed by the node and in a segment having a mirror relation with the segment managed by the node.

Abstract: A storage control device that is used for a storage system, the storage control device including a memory, and a processor configured to acquire a first access result by accessing a first logical storage area included in a combined logical storage area upon receiving a first access request for the combined logical area, the combined logical storage area being a logical storage area combined the first logical storage area and a second logical storage area, transmit a second access request for an unaccessed area in the combined logical storage area to another storage control device, and transmit, upon receiving a second access result corresponding to the second access request transmitted from the another storage control device, a third access result corresponding to the first access request to the access source device based on the first access result and the second access result.

Abstract: A storage system includes a first control apparatus; at least one second control apparatus managed by the first control apparatus; and a storage unit accessed by the second control apparatus. The second control apparatus determines based on detection of an error of an input/output process for storage in the storage unit whether the storage is in a blocking state, executes a resumption process of the input/output process when the storage is in the blocking state, judges whether an error occurrence frequency of the input/output process is at least a predetermined value, when the storage is not in the blocking state, and transmits to the first control apparatus, a blocking process request for the storage, when the error occurrence frequency is at least the predetermined value. The first control apparatus executes a blocking process and an error process of the storage, based on reception of the blocking process request.

Abstract: A virtualization controller identifies a node that manages a segment to be accessed, and instructs the node to access the segment. A mirror controller of the node instructed to access the segment writes data in the segment managed by the node and in a segment having a mirror relation with the segment managed by the node.

Abstract: A storage system includes a first control apparatus; at least one second control apparatus managed by the first control apparatus; and a storage unit accessed by the second control apparatus. The second control apparatus determines based on detection of an error of an input/output process for storage in the storage unit whether the storage is in a blocking state, executes a resumption process of the input/output process when the storage is in the blocking state, judges whether an error occurrence frequency of the input/output process is at least a predetermined value, when the storage is not in the blocking state, and transmits to the first control apparatus, a blocking process request for the storage, when the error occurrence frequency is at least the predetermined value. The first control apparatus executes a blocking process and an error process of the storage, based on reception of the blocking process request.

Abstract: A virtualization control apparatus includes a selection unit that, when receiving a copy request, conducting an access test corresponding to the copy request on each of the virtualization switch units and selects one of the virtualization switch units of the highest performance among the plurality of the virtual switch units, and a sending unit that sends the copy request to the selected virtualization switch unit.

Abstract: A virtualization control apparatus includes a selection unit that, when receiving a copy request, conducting an access test corresponding to the copy request on each of the virtualization switch units and selects one of the virtualization switch units of the highest performance among the plurality of the virtual switch units, and a sending unit that sends the copy request to the selected virtualization switch unit.

Abstract: A switch device includes interfaces connected to a host, a first storage device, and a second storage device having a cache memory, and a processor executing receiving a copy command indicating to copy target data stored in the first storage device to the second storage device from the host, transmitting a reading out command indicating to read out the target data stored in the first storage device corresponding to the copy command, receiving the target data corresponding to the transmitted reading out command from the first storage device, and transmitting, to the second storage device, a writing command for writing the target data and release information indicating that the target data is releasable from the cache memory.

Abstract: A display device capable of reducing screen flickering or flickers is dislcosed. More particularly, a technology for preventing an occurrence of flickers in the liquid-crystal display device of an active matrix type is disclosed. In a first frame, a drive voltage of a polarity determined in units of row based on a random number is applied. In a sequential second frame, a drive voltage of a polarity reverse to the polarity in the first frame is applied. The patterns of the polarities are alternately repeated.

Abstract: An image on a liquid crystal is displayed with a constant picture quality, independent of the capacity characteristic variations of the display and the conditions of signals for displaying an image. A gate-timing control circuit 50 of a drive circuit receives input signals J1, J2, and J3 from a system 44. The signals J1 and J2 are prestored in the timing-gate control circuit 50 and contain information for selecting any of a plurality of data, each representing different timing at which a gate line 28 of an LCD 10 is turned on and off. The timing control circuit 50 selects any of the plurality of data according to the signals J1 and J2, generates a gate line control signal YOE based upon the selected data, and outputs it to a gate line driver 30. The gate line driver 30 drives the gate line 28 at timing corresponding to the gate line control signal YOE.