Abstract: Provided is a reset system for resetting a plurality of registers in a data processing system. The system resets the registers to a predetermined pattern of "0's" and "1's" that is determined by the positioning of the registers along a data scan path. A group of registers to be reset to "0" are serially connected and a group of registers to be reset to "1" are similarly serially connected. An inversion gate is provided in the serial path between the group of registers to be reset to "0" and the group to be reset to "1". Each register is comprised of two latches which can each be enabled such that data can propagate through the entire scan path without requiring multiple clock transitions. In order to reset the system, the enable signals for the latches are asserted. Thereafter, an initial reset value is scanned into a first register of the scan path and propagates through the entire path.