Patents by Inventor Yasuhito Saito
Yasuhito Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9401398Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.Type: GrantFiled: July 14, 2015Date of Patent: July 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takeru Matsuoka, Yasuhito Saito, Seiichi Kamiyama
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Publication number: 20150318392Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.Type: ApplicationFiled: July 14, 2015Publication date: November 5, 2015Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
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Patent number: 9111771Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.Type: GrantFiled: September 22, 2014Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
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Publication number: 20150008510Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.Type: ApplicationFiled: September 22, 2014Publication date: January 8, 2015Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
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Patent number: 8872257Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.Type: GrantFiled: August 30, 2013Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
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Patent number: 8648246Abstract: According to one embodiment, a thermoelectric module includes a housing and a power generation member. The housing has a first temperature layer and a second temperature layer, the first temperature layer and the second temperature layer being stacked, the housing further having a cylindrical through-hole provided so as to penetrate the first temperature layer and the second temperature layer. The power generation member has thermoelectric materials stacked such that current flows in one direction in the power generation member, the power generation member being provided in the through-hole so that opposite ends of each of the thermoelectric materials are positioned at the first temperature layer and the second temperature layer, respectively.Type: GrantFiled: January 19, 2011Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Mio Ohmura, Jun Karasawa, Naruhito Kondo, Osamu Tsuneoka, Yasuhito Saito
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Publication number: 20120068357Abstract: According to one embodiment, a semiconductor device includes a base, a semiconductor element, an electrode terminal, a connecting member and a joining material. The semiconductor element is mounted on the base. The electrode terminal is provided spaced from the base. The connecting member connects the semiconductor element to the electrode terminal and includes a plurality of through holes provided in one end portion of the connecting member. The one end portion is connected to the semiconductor element. The joining material intervenes between the semiconductor element and the connecting member and penetrates into the plurality of through holes.Type: ApplicationFiled: September 16, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhito Saito, Masahiro Shimura
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Publication number: 20110247670Abstract: According to one embodiment, a thermoelectric module includes a housing and a power generation member. The housing has a first temperature layer and a second temperature layer, the first temperature layer and the second temperature layer being stacked, the housing further having a cylindrical through-hole provided so as to penetrate the first temperature layer and the second temperature layer. The power generation member has thermoelectric materials stacked such that current flows in one direction in the power generation member, the power generation member being provided in the through-hole so that opposite ends of each of the thermoelectric materials are positioned at the first temperature layer and the second temperature layer, respectively.Type: ApplicationFiled: January 19, 2011Publication date: October 13, 2011Inventors: Mio OHMURA, Jun Karasawa, Naruhito Kondo, Osamu Tsuneoka, Yasuhito Saito
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Publication number: 20100101619Abstract: There is provided a thermoelectric device capable of improving a power generation performance while keeping a hermetic sealing after a heat cycle is applied, and also achieving simplification of a structure and improvement in productivity and reliability of a device by reducing the number of articles, and a method of manufacturing the same. A thermoelectric device, includes a metal substrate 2, a thermoelectric element 3 mounted on a center portion of a surface of the metal substrate 2, a metal lid 4 for covering an upper surface and side surfaces of the thermoelectric element 3, and a joining metal member 5 provided to a peripheral portion of a surface of the metal substrate 2 to hermetically seal a space between the metal substrate 2 and the lid 4.Type: ApplicationFiled: January 5, 2010Publication date: April 29, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Takahiro SOGOU, Kazuki Tateyama, Hiroyoshi Hanada, Yasuhito Saito, Masayuki Arakawa, Naruhito Kondo, Osamu Tsuneoka, Naokazu Iwanade
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Patent number: 7633153Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: GrantFiled: July 16, 2007Date of Patent: December 15, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Patent number: 7514783Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: GrantFiled: August 31, 2005Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Publication number: 20080163916Abstract: According to one embodiment, a thermoelectric conversion module includes a thermoelectric conversion portion, a first external electrode, and a second external electrode. The thermoelectric conversion portion includes a single thermoelectric conversion portion element, or electrically connected thermoelectric conversion portion elements. The thermoelectric conversion portion element includes a high temperature electrode, low temperature electrodes, and an n-type and a p-type thermoelectric conversion semiconductor layer disposed between the high temperature electrode and the low temperature electrodes. The first and the second external electrode are electrically connected to one of the low temperature electrode and another one of the low temperature electrode respectively.Type: ApplicationFiled: October 22, 2007Publication date: July 10, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Osamu Tsuneoka, Naruhito Kondo, Akihiro Hara, Kazuki Tateyama, Takahiro Sogou, Yasuhito Saito, Masayuki Arakawa
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Publication number: 20080044897Abstract: A gene silencing vector according to the present invention comprises a vector which includes a promoter, an enhancer sequence in the downstream of the promoter, and a gene encoding a potyvirus-origin coat protein in the downstream of the enhancer sequence, wherein in order to cause gene silencing of the specific target gene in a host plant, the vector is used with a specific target gene or a gene that is homologous to the target gene inserted in the vicinity of the gene encoding the coat protein.Type: ApplicationFiled: October 18, 2007Publication date: February 21, 2008Applicant: JAPAN TABACCO INC.Inventors: Keisuke Kasaoka, Yasuhito Saito, Shigeru Kuwata
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Publication number: 20070256427Abstract: In order to provide a highly reliable thermoelectric device, in a thermoelectric device, a plurality of heat-radiating-side electrodes, arranged in accordance with positions where respective thermoelectric elements are to be arranged, are arrayed in an array fashion on a planer surface of a heat-radiating-side board. Heat-radiating-side end surfaces of the plurality of p-type thermoelectric elements and n-type thermoelectric elements and the heat-radiating-side electrodes are joined together by solders. Heat-absorbing-side electrodes are brought into sliding contact with heat-absorbing-side end surfaces of these thermoelectric elements.Type: ApplicationFiled: March 30, 2007Publication date: November 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuki Tateyama, Takahiro Sogou, Tomohiro Iguchi, Yasuhito Saito, Masayuki Arakawa, Naruhito Kondo, Osamu Tsuneoka, Akihiro Hara
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Publication number: 20070257708Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: ApplicationFiled: July 16, 2007Publication date: November 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Publication number: 20070257376Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: ApplicationFiled: July 16, 2007Publication date: November 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Patent number: 7278199Abstract: In order to provide a highly reliable thermoelectric device, in a thermoelectric device, a plurality of heat-radiating-side electrodes, arranged in accordance with positions where respective thermoelectric elements are to be arranged, are arrayed in an array fashion on a planer surface of a heat-radiating-side board. Heat-radiating-side end surfaces of the plurality of p-type thermoelectric elements and n-type thermoelectric elements and the heat-radiating-side electrodes are joined together by solders. Heat-absorbing-side electrodes are brought into sliding contact with heat-absorbing-side end surfaces of these thermoelectric elements.Type: GrantFiled: February 1, 2006Date of Patent: October 9, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Kazuki Tateyama, Takahiro Sogou, Tomohiro Iguchi, Yasuhito Saito, Masayuki Arakawa, Naruhito Kondo, Osamu Tsuneoka, Akihiro Hara
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Publication number: 20070028955Abstract: There is provided a thermoelectric device capable of improving a power generation performance while keeping a hermetic sealing after a heat cycle is applied, and also achieving simplification of a structure and improvement in productivity and reliability of a device by reducing the number of articles, and a method of manufacturing the same. A thermoelectric device, includes a metal substrate 2, a thermoelectric element 3 mounted on a center portion of a surface of the metal substrate 2, a metal lid 4 for covering an upper surface and side surfaces of the thermoelectric element 3, and a joining metal member 5 provided to a peripheral portion of a surface of the metal substrate 2 to hermetically seal a space between the metal substrate 2 and the lid 4.Type: ApplicationFiled: July 28, 2006Publication date: February 8, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Takahiro Sogou, Kazuki Tateyama, Hiroyoshi Hanada, Yasuhito Saito, Masayuki Arakawa, Naruhito Kondo, Osamu Tsuneoka, Naokazu Iwanade
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Publication number: 20060123799Abstract: In order to provide a highly reliable thermoelectric device, in a thermoelectric device, a plurality of heat-radiating-side electrodes, arranged in accordance with positions where respective thermoelectric elements are to be arranged, are arrayed in an array fashion on a planer surface of a heat-radiating-side board. Heat-radiating-side end surfaces of the plurality of p-type thermoelectric elements and n-type thermoelectric elements and the heat-radiating-side electrodes are joined together by solders. Heat-absorbing-side electrodes are brought into sliding contact with heat-absorbing-side end surfaces of these thermoelectric elements.Type: ApplicationFiled: February 1, 2006Publication date: June 15, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuki Tateyama, Takahiro Sogou, Tomohiro Iguchi, Yasuhito Saito, Masayuki Arakawa, Naruhito Kondo, Osamu Tsuneoka, Akihiro Hara
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Patent number: 7024865Abstract: In order to provide a highly reliable thermoelectric device, in a thermoelectric device, a plurality of heat-radiating-side electrodes, arranged in accordance with positions where respective thermoelectric elements are to be arranged, are arrayed in an array fashion on a planer surface of a heat-radiating-side board. Heat-radiating-side end surfaces of the plurality of p-type thermoelectric elements and n-type thermoelectric elements and the heat-radiating-side electrodes are joined together by solders. Heat-absorbing-side electrodes are brought into sliding contact with heat-absorbing-side end surfaces of these thermoelectric elements.Type: GrantFiled: July 23, 2004Date of Patent: April 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazuki Tateyama, Takahiro Sogou, Tomohiro Iguchi, Yasuhito Saito, Masayuki Arakawa, Naruhito Kondo, Osamu Tsuneoka, Akihiro Hara