Patents by Inventor Yasuji Ikeda

Yasuji Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9549139
    Abstract: The imaging apparatus has a plurality of pixels each of which has a plurality of photoelectric conversion units; generates a plurality of first combined signals obtained by combining signals based on electric charges of photoelectric conversion units in one side with each other, and a plurality of second signals obtained by combining signals based on electric charges of the plurality of photoelectric conversion units with each other; and outputs a part of the first combined signals out of the plurality of first combined signals.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: January 17, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuji Ikeda, Hiroki Hiyama, Yu Arishima, Seiji Hashimoto
  • Patent number: 9538110
    Abstract: A driving method of an imaging device, and a driving method of an imaging system set the number of unit cells based on signals output from a plurality of unit cells in a phase difference detection area within an imaging area to a number larger than the number of unit cells based on signals output from a plurality of unit cells in a range other than the phase difference detection area within the imaging area.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: January 3, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuji Ikeda
  • Publication number: 20160286148
    Abstract: In a photoelectric conversion apparatus, the number of differential transistors in which ON states thereof overlap with one another is increased when the number of the amplification transistors in which ON states thereof overlap with one another is increased.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 29, 2016
    Inventors: Kazuki Ohshitanai, Yasuji Ikeda
  • Patent number: 9438839
    Abstract: A solid state imaging apparatus includes: a pixel array in which pixels having color filters are arrayed in a matrix shape in accordance with a predetermined color arrangement, with each pixel including a plurality of divided pixels having a color filter of the same color; and an adding circuit that performs addition averaging of a plurality of signals output from the divided pixels included in a plurality of pixels having color filters of the same color. Among a plurality of pixels that are an object of the addition averaging, a number of signals output from the respective divided pixels of which the adding circuit performs addition averaging is different for at least one pixel relative to the other pixels.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: September 6, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Hiyama, Yasuji Ikeda
  • Patent number: 9344652
    Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 17, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
  • Patent number: 9270913
    Abstract: The present disclosure relate to photoelectric conversion apparatus and imaging system. The photoelectric conversion apparatus has a plurality of pixels arranged in rows and columns, and each configured to generate a signal by photoelectric conversion, a plurality of holding capacitors arranged correspondingly to the respective columns of the plurality of pixels, and configured to hold signals based on the pixels, a first output line, a second output line, a first switch arranged between the holding capacitor and the first output line, a second switch arranged between the holding capacitor and the second output line, and a column selecting line configured to control the second switch, wherein a wiring structure of a portion at which the column selecting line intersects the first output line is different from a wiring structure of a portion at which the column selecting line intersects the second output line.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 23, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Hiyama, Yasuji Ikeda
  • Patent number: 9258505
    Abstract: Provided is an imaging apparatus that generates a signal based on the sum of signals output by a plurality of pixels, and a signal based on the difference between the signals output by the plurality of signals, and performs AD conversion on the generated signals.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: February 9, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuji Ikeda
  • Patent number: 9159750
    Abstract: An image sensor comprises plural sets of a unit pixel outputting a pixel signal based on an electric charge generated through photoelectric conversion and a conversion unit converting the pixel signal into a digital signal. A reference signal source generates reference signals and supplies the generated reference signals to the conversion unit through signal lines. The conversion unit of each set comprises a comparator which compares the level of the reference signal with that of the pixel signal, a count circuit which counts a clock based on the comparison processing, a selection circuit which selects, among the signal lines, a signal line to be selectively connected to the input of the comparator, and a switch which selectively connects the selected signal line to the input of the comparator, and selectively connects a load to an unselected one of the signal lines.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 13, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuji Ikeda, Seiji Hashimoto, Takashi Muto, Yasushi Matsuno, Daisuke Yoshida
  • Publication number: 20150189249
    Abstract: A solid state imaging apparatus includes: a pixel array in which pixels having color filters are arrayed in a matrix shape in accordance with a predetermined color arrangement, with each pixel including a plurality of divided pixels having a color filter of the same color; and an adding circuit that performs addition averaging of a plurality of signals output from the divided pixels included in a plurality of pixels having color filters of the same color. Among a plurality of pixels that are an object of the addition averaging, a number of signals output from the respective divided pixels of which the adding circuit performs addition averaging is different for at least one pixel relative to the other pixels.
    Type: Application
    Filed: December 9, 2014
    Publication date: July 2, 2015
    Inventors: Hiroki Hiyama, Yasuji Ikeda
  • Publication number: 20150062102
    Abstract: A driving method of an imaging device, and a driving method of an imaging system set the number of unit cells based on signals output from a plurality of unit cells in a phase difference detection area within an imaging area to a number larger than the number of unit cells based on signals output from a plurality of unit cells in a range other than the phase difference detection area within the imaging area.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 5, 2015
    Inventor: Yasuji Ikeda
  • Publication number: 20150062394
    Abstract: The imaging apparatus has a plurality of pixels each of which has a plurality of photoelectric conversion units; generates a plurality of first combined signals obtained by combining signals based on electric charges of photoelectric conversion units in one side with each other, and a plurality of second signals obtained by combining signals based on electric charges of the plurality of photoelectric conversion units with each other; and outputs a part of the first combined signals out of the plurality of first combined signals.
    Type: Application
    Filed: August 6, 2014
    Publication date: March 5, 2015
    Inventors: Yasuji Ikeda, Hiroki Hiyama, Yu Arishima, Seiji Hashimoto
  • Patent number: 8969771
    Abstract: An imaging system includes an A/D converter including a holding unit holding a pixel signal as a voltage level, a comparator comparing the voltage level held with a reference level, a circuit capable of changing the voltage level so as to approach the reference level at first and second rates, wherein the voltage level is changed at the first rate to determine higher bits in accordance with inversion of a relationship between the reference level and the voltage level, after that, the voltage level is changed at the second rate to determine lower bits in accordance with inversion of the relationship between the reference level and the voltage level, and an adjusting unit which adjusts the voltage level during a period until the voltage level is changed at the second rate after determination of the higher bits so that the lower bits and the voltage level hold a linear relationship.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuji Ikeda, Hiroki Hiyama, Kazuo Yamazaki
  • Publication number: 20150042856
    Abstract: An imaging apparatus includes: a pixel configured to generate a signal through photoelectric conversion; a comparator configured to compare a signal generated by the pixel with a first reference signal that changes with time; and a control unit configured to change a change rate of the first reference signal with respect to time according to a comparison result of the comparator.
    Type: Application
    Filed: June 24, 2014
    Publication date: February 12, 2015
    Inventors: Kohichi Nakamura, Yasuji Ikeda
  • Publication number: 20150036032
    Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
  • Publication number: 20140368707
    Abstract: Provided is an imaging apparatus that generates a signal based on the sum of signals output by a plurality of pixels, and a signal based on the difference between the signals output by the plurality of signals, and performs AD conversion on the generated signals.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 18, 2014
    Inventor: Yasuji Ikeda
  • Publication number: 20140320717
    Abstract: The present disclosure relate to photoelectric conversion apparatus and imaging system. The photoelectric conversion apparatus has a plurality of pixels arranged in rows and columns, and each configured to generate a signal by photoelectric conversion, a plurality of holding capacitors arranged correspondingly to the respective columns of the plurality of pixels, and configured to hold signals based on the pixels, a first output line, a second output line, a first switch arranged between the holding capacitor and the first output line, a second switch arranged between the holding capacitor and the second output line, and a column selecting line configured to control the second switch, wherein a wiring structure of a portion at which the column selecting line intersects the first output line is different from a wiring structure of a portion at which the column selecting line intersects the second output line.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 30, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Hiyama, Yasuji Ikeda
  • Publication number: 20140312207
    Abstract: A solid-state imaging apparatus and an imaging system which can reduce the occurrence of darkening and decrease deterioration in CDS performance are provided. The solid-state imaging apparatus has: a pixel unit including a photoelectric conversion unit for generating a signal by a photoelectric conversion; an amplifier unit for amplifying the signal generated by the photoelectric conversion unit; and a limiting circuit for limiting a level of an output signal from the amplifier unit. The pixel unit outputs a noise signal under a reset state during a first period and outputs a pixel signal under a non-reset state during a second period. The limiting circuit limits the level of the output signal from the amplifier unit in the first period, lower than the level of the output signal from the amplifier unit in the second period.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 23, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuji Ikeda, Hiroki Hiyama
  • Patent number: 8785832
    Abstract: A solid-state imaging apparatus has: output lines connected commonly to each column of a plurality of pixels; a reference signal generating circuit for generating a reference signal voltage changing in a ramp shape; a comparator for comparing the reference signal voltage with an analog voltage on the output line; and a counter unit for counting, as a digital value, a period from a start of the comparing of the comparator until an inversion of an output signal of the comparator, wherein the reference signal generating circuit sets the reference signal voltage into an offset voltage, thereafter, an input terminal of the comparator is reset, thereafter, the reference signal generating circuit resets the reference signal voltage from the offset voltage into a initial voltage, and thereafter, the reference signal generating circuit generates the ramp-shaped reference signal voltage from the initial voltage, so that the comparator starts the comparing.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuji Ikeda
  • Publication number: 20120261552
    Abstract: A solid-state imaging apparatus has: output lines connected commonly to each column of a plurality of pixels; a reference signal generating circuit for generating a reference signal voltage changing in a ramp shape; a comparator for comparing the reference signal voltage with an analog voltage on the output line; and a counter unit for counting, as a digital value, a period from a start of the comparing of the comparator until an inversion of an output signal of the comparator, wherein the reference signal generating circuit sets the reference signal voltage into an offset voltage, thereafter, an input terminal of the comparator is reset, thereafter, the reference signal generating circuit resets the reference signal voltage from the offset voltage into a initial voltage, and thereafter, the reference signal generating circuit generates the ramp-shaped reference signal voltage from the initial voltage, so that the comparator starts the comparing.
    Type: Application
    Filed: March 8, 2012
    Publication date: October 18, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yasuji Ikeda
  • Publication number: 20120211643
    Abstract: An imaging system includes an A/D converter including a holding unit holding a pixel signal as a voltage level, a comparator comparing the voltage level held with a reference level, a circuit capable of changing the voltage level so as to approach the reference level at first and second rates, wherein the voltage level is changed at the first rate to determine higher bits in accordance with inversion of a relationship between the reference level and the voltage level, after that, the voltage level is changed at the second rate to determine lower bits in accordance with inversion of the relationship between the reference level and the voltage level, and an adjusting unit which adjusts the voltage level during a period until the voltage level is changed at the second rate after determination of the higher bits so that the lower bits and the voltage level hold a linear relationship.
    Type: Application
    Filed: December 20, 2010
    Publication date: August 23, 2012
    Applicant: Canon Kabushiki Kaisha
    Inventors: Yasuji Ikeda, Hiroki Hiyama, Kazuo Yamazaki