Patents by Inventor Yasukazu Ikeda

Yasukazu Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High frequency transistor with reduced parasitic inductance
    Patent number: 5635751
    Abstract: A semiconductor device includes a transistor mounted on a chip substrate. A metal sheet is disposed on the metallized electrode to which the base, for example, of the transistor is electrically connected. The base is electrically connected by a wire to the metal sheet. An MOS capacitor is disposed on the metal sheet and a through-hole beneath the metal sheet connects the metallized electrode directly to a metallized ground electrode disposed on the bottom surface of the substrate.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 3, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasukazu Ikeda, Hideo Matsumoto, Susumu Sakamoto
  • High frequency transistor with reduced parasitic inductance
    Patent number: 5465007
    Abstract: A semiconductor device includes a transistor mounted on the top surface of a substrate. A metal sheet is disposed on a metallized electrode on the substrate to which the emitter, for example, of the transistor is electrically connected. The emitter is electrically connected by a thin metal wire to the metal sheet. An MOS capacitor is disposed on the metal sheet, and a plated through-hole beneath the metal sheet connects the metallized electrode directly to a metallized ground electrode disposed on the bottom surface of the substrate.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: November 7, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasukazu Ikeda, Hideo Matsumoto, Susumu Sakamoto