Abstract: A semiconductor device includes a cylindrical capacitor having a bottom electrode, a capacitor insulator film and a top electrode. The top electrode includes first and second electrode portions insulated from each other and opposing the inner surface and outer surface, respectively, of the bottom electrode. The second electrode portion is deposited prior to the bottom electrode, preventing collapse of the bottom electrode during manufacture of the semiconductor device.

Abstract: The unit cell is constructed to have a volatile memory element provided with a capacitor element adapted to store and sustain an electric charge only in a state in which electric power is supplied, and a nonvolatile memory element adapted to save said electric charge stored in said capacitor element when the supply of said electric power is cut off. One end of said capacitor element is connected by way of said nonvolatile memory element to a potential supply line. Said nonvolatile memory element acts as a conductive element in a state in which said electric power is supplied and acts as a cut-off element in a state in which said electric power is not supplied, and in addition, has a threshold that varies in a case where the electric charge stored in said capacitor element corresponds to a predetermined potential level.

Abstract: A semiconductor memory device includes a plurality of memory cells, each of which comprises a single pair of a volatile memory element and a non-volatile memory element, wherein the volatile memory element and the non-volatile memory element are electrically coupled to each other, and wherein the volatile memory element is also electrically coupled to a first bit line for transmitting a first bit signal, while the non-volatile memory element is also electrically coupled to a second bit line making a single pair with the first bit line for transmitting a second bit signal which is an inversion to the first bit signal.

Abstract: A multi-chip-package (MCP) module includes a plurality of semiconductor chips layered one on another. The lower semiconductor chip includes a semiconductor substrate having a top active layer and a bottom heavily-doped layer. The bottom of the heavily-doped layer is polished twice by a rough-polishing treatment and a mirror-polishing treatment. The thickness of the impurity-doped layer is not less than 50% of the thickness of the semiconductor substrate which is not larger than 130 ?m.

Abstract: The unit cell is constructed to have a volatile memory element provided with a capacitor element adapted to store and sustain an electric charge only in a state in which electric power is supplied, and a nonvolatile memory element adapted to save said electric charge stored in said capacitor element when the supply of said electric power is cut off. One end of said capacitor element is connected by way of said nonvolatile memory element to a potential supply line. Said nonvolatile memory element acts as a conductive element in a state in which said electric power is supplied and acts as a cut-off element in a state in which said electric power is not supplied, and in addition, has a threshold that varies in a case where the electric charge stored in said capacitor element corresponds to a predetermined potential level.

Abstract: A semiconductor memory device includes a plurality of memory cells, each of which comprises a single pair of a volatile memory element and a non-volatile memory element, wherein the volatile memory element and the non-volatile memory element are electrically coupled to each other, and wherein the volatile memory element is also electrically coupled to a first bit line for transmitting a first bit signal, while the non-volatile memory element is also electrically coupled to a second bit line making a single pair with the first bit line for transmitting a second bit signal which is an inversion to the first bit signal.

Abstract: A semiconductor memory device having an improved storage capacitor is disclosed.

Abstract: A dynamic random access memory device including one-transistor type memory cells each having a trench capacitor is disclosed. An impurity region of a conductivity type opposite to the substrate and having a net-like plane shape is provided in an inner portion of the substrate, and the impurity region is led-out at a part to the major surface of the substrate. A trench is formed in the substrate from the major surface into the impurity region so that a wall section of the trench is constituted by the impurity region. A dielectric film of the capacitor is formed on the wall section, and a capacitor electrode is formed on the dielectric film and connected to source or drain region of the transistor.

Abstract: A semiconductor device having a wiring layer composed of a polycrystalline silicon film and an aluminum film is disclosed. The wiring layer is provided on an insulating layer with the silicon film and the aluminum film formed on and having the same pattern with the silicon film, and the aluminum film is directly contacted to an impurity region of a substrate without interposing the silicon film.

Abstract: A highly integrated semiconductor memory device having one transistor type memory cells is disclosed. The capacitor and transistor of the memory cell is provided within and around one trench formed in the semiconductor substrate. The channel region of the transistor is positioned along the side wall of the trench with a ring shape in the plan view and the capacitor element is surrounded by the transistor within the trench.

Abstract: An improved integrated circuit provided with a reduced capacitance of common external terminal connected to a plurality of circuits is disclosed. A switch is inserted between the external terminal and at least one of the circuits. The switch is controlled in such manner that it is rendered conductive when that circuit is to receive the signal at the external terminal and non-conductive when the circuit is not to receive the signal at the external terminal therein.

Abstract: An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption.A first switch is provided between a refresh voltage terminal and a true circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.

Abstract: An integrated circuit includes an insulated-gate field effect transistor and a protection device coupled to either the source or drain of the transistor. The protection device includes a gate-controlled diode having a breakdown voltage that is less than the breakdown voltage of the drain of the field effect transistor.

Abstract: A silicon layer is deposited over the insulating layer covering the surface of the semiconductor substrate and apertured to define a contact window through which the silicon layer is connected with a one-conductivity-type region formed in the semiconductor substrate. An impurity of the one conductivity type is introduced into the one-conductivity-type region through the contact window from the silicon layer. This impurity may be supplied from the surface of the silicon layer or may be preliminarily doped in the silicon layer. A conductive layer is deposited over the silicon layer and is formed to a predetermined pattern. Thereafter, the silicon layer is formed to the same pattern.