Patents by Inventor Yasuki Aihara
Yasuki Aihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240428666Abstract: A thermal image acquisition device (2) acquires a thermal image of a balcony (1). Setting circuitry (11) sets an outside area (15) corresponding to an outside of the balcony (1) and a balcony inside area (16) corresponding to inside of the balcony (1) in the thermal image. Heat source detection circuitry (9) detects a heat source (14) in the thermal image. Intrusion determination circuitry (12) determines that “there is an intrusion” if a central position of the heat source (14) with the number of pixels and a temperature equal to or greater than thresholds moves from the outside area (15) to the balcony inside area (16) in the thermal image. A determination result output device (13) outputs a determination result of the intrusion determination circuitry (12).Type: ApplicationFiled: December 21, 2021Publication date: December 26, 2024Applicant: Mitsubishi Electric CorporationInventors: Satoshi OKUDA, Masaharu HATTORI, Yasuki AIHARA, Takashi TAKENAGA
-
Publication number: 20240192057Abstract: A thermal image acquisitor (3) is attached to a wall (4) or a ceiling (5) on a side of a head of a care recipient (1) in a case where the care recipient lies on a bed (2), and captures an image of the bed and its surroundings from diagonally above to acquire a thermal image. Reference setting circuitry (12) sets two reference lines (8,9) respectively corresponding to a left end and a right end of the bed in the thermal image, and a reference height (10) for determining sitting-up of the care recipient. Heat source detection circuitry (13) detects a mass (11) of a heat source in the thermal image. State determination circuitry (14) determines a state of the care recipient from a positional relationship between a safe area (15) enclosed with the reference lines and the reference height and the mass of the heat source.Type: ApplicationFiled: September 15, 2021Publication date: June 13, 2024Applicant: Mitsubishi Electric CorporationInventors: Satoshi OKUDA, Masaharu HATTORI, Yasuki AIHARA, Takashi TAKENAGA, Kazuya SATO, Yasuaki SUSUMU, Kenichiro CHOMEI
-
Patent number: 11876061Abstract: Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.Type: GrantFiled: March 6, 2019Date of Patent: January 16, 2024Assignee: Mitsubishi Electric CorporationInventor: Yasuki Aihara
-
Publication number: 20220093544Abstract: Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.Type: ApplicationFiled: March 6, 2019Publication date: March 24, 2022Applicant: Mitsubishi Electric CorporationInventor: Yasuki AIHARA
-
Patent number: 10248023Abstract: A method of manufacturing a semiconductor device includes: coating a first resist containing a photoacid generator or a thermal acid generator on a semiconductor substrate; forming a first opening portion in the first resist by optical exposure; subjecting a shrink agent containing an acid to a crosslinking reaction by the heat treatment to form a thermoset layer on an overall surface of the first resist; coating a second resist on the semiconductor substrate and the thermoset layer; and forming a second opening portion located above the first opening portion and larger than the first opening portion in the second resist by optical exposure.Type: GrantFiled: February 19, 2018Date of Patent: April 2, 2019Assignee: Mitsubishi Electric CorporationInventors: Yasuki Aihara, Kazuyuki Onoe, Takahiro Ueno
-
Publication number: 20190079400Abstract: A method of manufacturing a semiconductor device includes: coating a first resist containing a photoacid generator or a thermal acid generator on a semiconductor substrate; forming a first opening portion in the first resist by optical exposure; subjecting a shrink agent containing an acid to a crosslinking reaction by the heat treatment to form a thermoset layer on an overall surface of the first resist; coating a second resist on the semiconductor substrate and the thermoset layer; and forming a second opening portion located above the first opening portion and larger than the first opening portion in the second resist by optical exposure.Type: ApplicationFiled: February 19, 2018Publication date: March 14, 2019Applicant: Mitsubishi Electric CorporationInventors: Yasuki AIHARA, Kazuyuki ONOE, Takahiro UENO
-
Patent number: 7768043Abstract: A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the semiconductor device is wholly covered by sealing resin.Type: GrantFiled: July 17, 2006Date of Patent: August 3, 2010Assignee: Mitsubishi Electric CorporationInventor: Yasuki Aihara
-
Patent number: 7625789Abstract: A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO2 film. A lower electrode of a MIM capacitor is formed on the GaAs substrate. The active portion of the field effect transistor is coated with a fluorine-containing polymer layer. A SiN film, which is a capacity insulating film of the MIM capacitor, is formed on the fluorine-containing polymer layer and the lower electrode. After removing the SiN film from the fluorine-containing polymer layer, the fluorine-containing polymer layer is selectively removed from the SiO2 film and the SiN film. An upper electrode of the MIM capacitor is formed opposite the lower electrode on the SiN film.Type: GrantFiled: January 7, 2008Date of Patent: December 1, 2009Assignee: Mitsubishi Electric CorporationInventor: Yasuki Aihara
-
Publication number: 20080280400Abstract: A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO2 film. A lower electrode of a MIM capacitor is formed on the GaAs substrate. The active portion of the field effect transistor is coated with a fluorine-containing polymer layer. A SiN film, which is a capacity insulating film of the MIM capacitor, is formed on the fluorine-containing polymer layer and the lower electrode. After removing the SiN film from the fluorine-containing polymer layer, the fluorine-containing polymer layer is selectively removed from the SiO2 film and the SiN film. An upper electrode of the MIM capacitor is formed opposite the lower electrode on the SiN film.Type: ApplicationFiled: January 7, 2008Publication date: November 13, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Yasuki Aihara
-
Publication number: 20070123026Abstract: A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the semiconductor device is wholly covered by sealing resin.Type: ApplicationFiled: July 17, 2006Publication date: May 31, 2007Applicant: Mitsubishi Electric CorporationInventor: Yasuki Aihara
-
Publication number: 20060086997Abstract: A buffer layer made of i-GaAs not doped with impurities, and an n+ GaAs layer doped with a high-concentration of n-type impurities are stacked in the order named on a semi-insulating GaAs substrate. An n? GaAs layer doped with a low-concentration of n-type impurities is partially located on the n+ GaAs layer. Cathode electrodes are located in opening regions in which the n? GaAs layer is not present on the n+ GaAs layer. An anode electrode is located on the n? GaAs layer. The n+ GaAs layer has a carrier concentration of 5×1018 cm?3, and is in ohmic contact with the cathode electrodes. The n? GaAs layer has a carrier concentration of 1.2×1017 cm?3, and is in Schottky contact with the anode electrode.Type: ApplicationFiled: September 27, 2005Publication date: April 27, 2006Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Koh Kanaya, Yasuki Aihara