Patents by Inventor Yasuki Takata

Yasuki Takata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9230937
    Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
  • Patent number: 8415245
    Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: April 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuki Takata, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa
  • Publication number: 20120286427
    Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Inventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
  • Publication number: 20110057299
    Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 10, 2011
    Inventors: Yasuki TAKATA, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa
  • Patent number: 7763966
    Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
  • Publication number: 20080217750
    Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
  • Publication number: 20050212103
    Abstract: A semiconductor device includes a semiconductor chip, an inner lead and a wire interconnecting a pad of the semiconductor chip with the inner lead. The wire is formed such that the eigenfrequency of the loop is outside a predetermined range of an ultrasonic vibration frequency used to form the loop. Accordingly, a rupture or break of a wire due to the resonance of a loop can be prevented.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 29, 2005
    Inventor: Yasuki Takata
  • Publication number: 20040262723
    Abstract: At least one of a corner portion of the semiconductor chip, a corner portion of the sealing member, and a portion in which two neighboring gold wires are spaced at a larger distance than any other two neighboring gold wires adjacent to the two neighboring gold wires is configured such that one electrode and another electrode adjacent to it are arranged in such a way that the space between one gold wire connected to one electrode and another gold wire connected to another electrode and adjacent to one gold wire is substantially equal to the diameter of these gold wires when one gold wire has been displaced toward another gold wire due to a flow of a resin at a time of sealing with the resin.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 30, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Zhikang Qin, Yasuki Takata, Hiroshi Horibe, Fumiaki Aga, Noriaki Higuchi, Yasuhito Suzuki
  • Patent number: 6518652
    Abstract: A semiconductor package includes a semiconductor chip, a die pad, an adhesive, metal wires, LOC inner leads, and standard inner leads sealed within a sealing resin. The LOC inner leads and the standard inner leads are arranged in the same plane and both are arranged along one side of the semiconductor chip. Clearance between the inner leads and the die pad larger than the total thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed can be employed and the section modulus of the semiconductor package can be increased.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: February 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuki Takata, Hiroshi Horibe, Kazunari Michii
  • Publication number: 20020027279
    Abstract: The present invention provides a semiconductor package in which a semiconductor chip, a die pad, an adhesive, metal wires, LOC type inner and standard type inner leads are sealed with a sealing resin. The LOC type inner leads and the standard type inner leads are arranged on a same plane and mixedly arranged along a side of the semiconductor chip. Clearance between the inner leads and the die pad is set to be larger than a sum of thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed and arranged thereon can be employed and the modulus of section of the semiconductor package can be enhanced.
    Type: Application
    Filed: March 15, 2001
    Publication date: March 7, 2002
    Inventors: Yasuki Takata, Hiroshi Horibe, Kazunari Michii