Patents by Inventor Yasukichi Ohkawa

Yasukichi Ohkawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8266476
    Abstract: To provide a multiprocessor system in which data transmission efficiency is unlikely to be affected if a damaged processor should exist among a plurality of processors. The multiprocessor system has a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, and specifies at least one damaged processor; selects as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus; and restricts data transmission by the communication restricted processor via the bus.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: September 11, 2012
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Tsutomu Horikawa, Yasukichi Ohkawa
  • Patent number: 8028284
    Abstract: A system is provided having a group of processors which performs coordinated processing, wherein data is transferred to the group of processors or from the group of processors. When data is transferred from an input queue, a ring buffer, to the group of processors, an identifier adding unit adds an identifier to the data as a tag, the identifier indicating a block that contains this data in the input queue. When data processed by any one of the processors included in the group of processors is transferred to an output queue, a block selecting unit selects one of blocks of the output queue as a block for storing the data, the one corresponding to the tag added to this data.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: September 27, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Yasukichi Ohkawa
  • Patent number: 7904618
    Abstract: A buffer is provided with a leading pointer and a following pointer. A bitmap in which two bits are assigned to each block is updated to retain which states blocks are in, busy, write-completed, or read-completed. Under the constraint that the two pointers move in the same direction and do not pass each other: after the block designated by the leading pointer starts to be written, the leading pointer is moved to a next block only if the next block is in the read-completed state; and after the block designated by the following pointer starts to be read, the following pointer is moved to a next block only if the next block is in the write-completed state.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 8, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Keisuke Inoue, Yasukichi Ohkawa
  • Publication number: 20100023665
    Abstract: To provide a multiprocessor system in which data transmission efficiency is unlikely to be affected if a damaged processor should exist among a plurality of processors. The multiprocessor system has a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, and specifies at least one damaged processor; selects as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus; and restricts data transmission by the communication restricted processor via the bus.
    Type: Application
    Filed: September 26, 2007
    Publication date: January 28, 2010
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Tsutomu Horikawa, Yasukichi Ohkawa
  • Publication number: 20090043927
    Abstract: A buffer is provided with a leading pointer and a following pointer. A bitmap in which two bits are assigned to each block is updated to retain which states blocks are in, busy, write-completed, or read-completed. Under the constraint that the two pointers move in the same direction and do not pass each other: after the block designated by the leading pointer starts to be written, the leading pointer is moved to a next block only if the next block is in the read-completed state; and after the block designated by the following pointer starts to be read, the following pointer is moved to a next block only if the next block is in the write-completed state.
    Type: Application
    Filed: May 31, 2006
    Publication date: February 12, 2009
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Keisuke Inoue, Yasukichi Ohkawa
  • Publication number: 20070106844
    Abstract: A system is provided having a group of processors which performs coordinated processing, wherein data is transferred to the group of processors or from the group of processors. When data is transferred from an input queue, a ring buffer, to the group of processors, an identifier adding unit adds an identifier to the data as a tags the identifier indicating a block that contains this data in the input queue. When data processed by any one of the processors included in the group of processors is transferred to an output queue, a block selecting unit selects one of blocks of the output queue as a block for storing the data, the one corresponding to the tag added to this data.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 10, 2007
    Inventor: Yasukichi Ohkawa