Patents by Inventor Yasuko ECKERT

Yasuko ECKERT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220100563
    Abstract: A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting operating condition; undarken the physical compute resource responsive to detecting the activation-warranting operating condition; detect a configuration-warranting operating condition; and configure the overprovisioned microprocessor to use the undarkened physical compute resource responsive to detecting the configuration-warranting operating condition.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Anthony Gutierrez, Vedula Venkata Srikant Bharadwaj, Yasuko Eckert, Mark H. Oskin
  • Publication number: 20220091980
    Abstract: A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Onur Kayiran, Yasuko Eckert, Mark Henry Oskin, Gabriel H. Loh, Steven E. Raasch, Maxim V. Kazakov
  • Patent number: 11226900
    Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 18, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William Louie Walker, Michael Warren Boyer
  • Publication number: 20210312952
    Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 7, 2021
    Inventors: Nuwan S. JAYASENA, Yasuko ECKERT
  • Publication number: 20210255871
    Abstract: A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit, determining that between the first cycle and the second cycle, no quantum operations are performed in the second quantum processing region, and moving the qubit from the first quantum processing region to the second quantum processing region.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Onur Kayiran, Jieming Yin, Yasuko Eckert
  • Publication number: 20210232501
    Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 29, 2021
    Inventors: Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William Louie Walker, Michael Warren Boyer
  • Publication number: 20210224130
    Abstract: Methods and systems for load balancing in a neural network system using metadata are disclosed. Any one or a combination of one or more kernels, one or more neurons, and one or more layers of the neural network system are tagged with metadata. A scheduler detects whether there are neurons that are available to execute. The scheduler uses the metadata to schedule and load balance computations across compute resources and available resources.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Nicholas Malaya, Yasuko Eckert
  • Patent number: 11068458
    Abstract: A portion of a graph dataset is generated for each computing node in a distributed computing system by, for each subject vertex in a graph, recording for the computing node an offset for the subject vertex, where the offset references a first position in an edge array for the computing node, and for each edge of a set of edges coupled with the subject vertex in the graph, calculating an edge value for the edge based on a connected vertex identifier identifying a vertex coupled with the subject vertex via the edge. When the edge value is assigned to the first position, the edge value is determined by a first calculation, and when the edge value is assigned to position subsequent to the first position, the edge value is determined by a second calculation. In the computing node, the edge value is recorded in the edge array.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 20, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert
  • Publication number: 20210182234
    Abstract: Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Majed Valad Beigi, Yasuko Eckert, Dongping Zhang
  • Publication number: 20210182193
    Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Weon Taek NA, Jagadish B. KOTRA, Yasuko ECKERT, Steven RAASCH, Sergey BLAGODUROV
  • Publication number: 20210182213
    Abstract: Systems, apparatuses, and methods for implementing cache line re-reference interval prediction using a physical page address are disclosed. When a cache line is accessed, a controller retrieves a re-reference interval counter value associated with the line. If the counter is less than a first threshold, then the address of the cache line is stored in a small re-use page buffer. If the counter is greater than a second threshold, then the address is stored in a large re-use page buffer. When a new cache line is inserted in the cache, if its address is stored in the small re-use page buffer, then the controller assigns a high priority to the line to cause it to remain in the cache to be re-used. If a match is found in the large re-use page buffer, then the controller assigns a low priority to the line to bias it towards eviction.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Jieming Yin, Yasuko Eckert, Subhash Sethumurugan
  • Publication number: 20210182216
    Abstract: Systems, apparatuses, and methods for cache management based on access type priority are disclosed. A system includes at least a processor and a cache. During a program execution phase, certain access types are more likely to cause demand hits in the cache than others. Demand hits are load and store hits to the cache. A run-time profiling mechanism is employed to find which access types are more likely to cause demand hits. Based on the profiling results, the cache lines that will likely be accessed in the future are retained based on their most recent access type. The goal is to increase demand hits and thereby improve system performance. An efficient cache replacement policy can potentially reduce redundant data movement, thereby improving system performance and reducing energy consumption.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Jieming Yin, Yasuko Eckert, Subhash Sethumurugan
  • Publication number: 20210173796
    Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Sooraj Puthoor, Kishore Punniyamurthy, Onur Kayiran, Xianwei Zhang, Yasuko Eckert, Johnathan Alsop, Bradford Michael Beckmann
  • Patent number: 10984838
    Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 20, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan S. Jayasena, Yasuko Eckert
  • Publication number: 20210109861
    Abstract: A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the cache, wherein the reuse distance represents an average number of accesses to a given cache set of the region between accesses to any given cache line of the cache set.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Inventors: Jieming YIN, Subhash SETHUMURUGAN, Yasuko ECKERT
  • Patent number: 10970120
    Abstract: Methods and systems for opportunistic load balancing in deep neural networks (DNNs) using metadata. Representative computational costs are captured, obtained or determined for a given architectural, functional or computational aspect of a DNN system. The representative computational costs are implemented as metadata for the given architectural, functional or computational aspect of the DNN system. In an implementation, the computed computational cost is implemented as the metadata. A scheduler detects whether there are neurons in subsequent layers that are ready to execute. The scheduler uses the metadata and neuron availability to schedule and load balance across compute resources and available resources.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: April 6, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nicholas Malaya, Yasuko Eckert
  • Patent number: 10938709
    Abstract: A method includes receiving, from an origin computing node, a first communication addressed to multiple destination computing nodes in a processor interconnect fabric, measuring a first set of one or more communication metrics associated with a transmission path to one or more of the multiple destination computing nodes, and for each of the destination computing nodes, based on the set of communication metrics, selecting between a multicast transmission mode and unicast transmission mode as a transmission mode for transmitting the first communication to the destination computing node.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 2, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Jieming Yin
  • Patent number: 10853904
    Abstract: A processor employs a hierarchical register file for a graphics processing unit (GPU). A top level of the hierarchical register file is stored at a local memory of the GPU (e.g., a memory on the same integrated circuit die as the GPU). Lower levels of the hierarchical register file are stored at a different, larger memory, such as a remote memory located on a different die than the GPU. A register file control module monitors the status of in-flight wavefronts at the GPU, and in particular whether each in-flight wavefront is active, predicted to be become active, or inactive. The register file control module places execution data for active and predicted-active wavefronts in the top level of the hierarchical register file and places execution data for inactive wavefronts at lower levels of the hierarchical register file.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 1, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yasuko Eckert, Nuwan Jayasena
  • Patent number: 10838864
    Abstract: A miss in a cache by a thread in a wavefront is detected. The wavefront includes a plurality of threads that are executing a memory access request concurrently on a corresponding plurality of processor cores. A priority is assigned to the thread based on whether the memory access request is addressed to a local memory or a remote memory. The memory access request for the thread is performed based on the priority. In some cases, the cache is selectively bypassed depending on whether the memory access request is addressed to the local or remote memory. A cache block is requested in response to the miss. The cache block is biased towards a least recently used position in response to requesting the cache block from the local memory and towards a most recently used position in response to requesting the cache block from the remote memory.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 17, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael W. Boyer, Onur Kayiran, Yasuko Eckert, Steven Raasch, Muhammad Shoaib Bin Altaf
  • Publication number: 20200293445
    Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Mohamed Assem IBRAHIM, Onur KAYIRAN, Yasuko ECKERT, Gabriel H. LOH