Abstract: A method may include, in response to a change in an operating parameter of a processing unit, modifying a signal pathway to a processing circuit component of the processing unit, and communicating with the processing circuit component via the signal pathway.

Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.

Abstract: In aspects of near-memory random and pattern-based data generation, a system includes a number generator circuit configured to generate a sequence of numbers, a memory chip configured to store the sequence of numbers, and a memory interface configured to enable communication between the number generator circuit and the memory chip. In one or more implementations, the number generator circuit includes a random number generator circuit configured to generate the sequence of numbers as a sequence of random numbers. Additionally, or alternatively, the number generator circuit includes a pattern fill function configured to generate the sequence of numbers based on a pattern. In other aspects of near-memory random and pattern-based data generation, a memory device includes a base layer, a memory interface, and a number generator circuit interleaved among the base layer and the memory interface.

Abstract: A method for executing an instruction by an arithmetic logic unit pipeline can include performing, by permutation circuitry, a permutation in response to an instruction that includes an arithmetic operation. The method can also include performing, by an arithmetic logic unit, the arithmetic operation in response to the instruction. Various other methods and systems are also disclosed.

Abstract: A system and method for efficiently accessing sparse data for a workload are described. In various implementations, a computing system includes an integrated circuit and a memory for storing tasks of a workload that includes sparse accesses of data items stored in one or more tables. The integrated circuit receives a user query, and generates a result based on multiple data items targeted by the user query. To reduce the latency of processing the workload even with sparse lookup operations performed on the one or more tables, a prefetch engine of the integrated circuit stores a subset of data items in prefetch data storage. The prefetch engine also determines which data items to store in the prefetch data storage based on one or more of a frequency of reuse, a distance or latency of access of a corresponding table of the one more tables, or other.

Abstract: An electronic device includes processing circuitry that executes a lookup table (LUT) vector instruction. Executing the lookup table vector instruction causes the processing circuitry to acquire a set of reference values by using each input value from an input vector as an index to acquire a reference value from a reference vector. The processing circuitry then provides the set of reference values for one or more subsequent operations. The processing circuitry can also use the set of reference values for controlling vector elements from among a set of vector elements for which a vector operation is performed.

Abstract: The disclosed computing device can identify multiple loads, from contiguous memory locations into respective registers, that have been fused into a load instruction sequence. The computing device can split the contiguous memory locations into separate load instructions for each register to generate a split load instruction sequence that replaces the fused load instruction sequence. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Abstract: Systems, apparatuses, and methods for implementing cache line re-reference interval prediction using a physical page address are disclosed. When a cache line is accessed, a controller retrieves a re-reference interval counter value associated with the line. If the counter is less than a first threshold, then the address of the cache line is stored in a small re-use page buffer. If the counter is greater than a second threshold, then the address is stored in a large re-use page buffer. When a new cache line is inserted in the cache, if its address is stored in the small re-use page buffer, then the controller assigns a high priority to the line to cause it to remain in the cache to be re-used. If a match is found in the large re-use page buffer, then the controller assigns a low priority to the line to bias it towards eviction.

Abstract: A disclosed method for consolidating eligible vector instructions can include detecting a plurality of vector instructions within a queue of an integrated circuit. The method can also include consolidating the plurality of vector instructions into a single vector instruction based at least in part on the plurality of instructions satisfying one or more criteria. The method can further include forwarding the single vector instruction through a pipeline of the integrated circuit. Various other devices, systems, and methods are also disclosed.

Abstract: The disclosed device includes various components; and a control circuit for managing performance states of the components. The control circuit can receive an event trigger corresponding to one of the components, monitor an activity metric for the component, and update a performance state of the component based on the event trigger and the activity metric. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for collapsing operations into super operations in a computing system includes dispatching a super operation corresponding to a collapsible sequence of operations to a scheduler, performing a lookup in a super operation table for the collapsible sequence of operations in response to the super operation being picked from the scheduler, and multi-pumping the collapsible sequence of operations to a pipe operationally coupled to the scheduler. For example, the multi-pumped collapsible sequence of operations may then be sequentially executed by an execution unit. The collapsible sequence of operations may be identified as collapsible according to a set of rules.

Abstract: An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

Abstract: An electronic device includes processing circuitry that executes a lookup table (LUT) vector instruction. Executing the lookup table vector instruction causes the processing circuitry to acquire a set of reference values by using each input value from an input vector as an index to acquire a reference value from a reference vector. The processing circuitry then provides the set of reference values for one or more subsequent operations. The processing circuitry can also use the set of reference values for controlling vector elements from among a set of vector elements for which a vector operation is performed.

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

Abstract: A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit, determining that between the first cycle and the second cycle, no quantum operations are performed in the second quantum processing region, and moving the qubit from the first quantum processing region to the second quantum processing region.

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.