Patents by Inventor Yasuko Tonomura
Yasuko Tonomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8248838Abstract: A semiconductor device includes a comparison unit for comparing a resistance value of a memory element selectively connected to an input terminal with a resistance value of a reference resistance, and a resistance reference unit capable of selecting one of a plurality of resistance values and capable of being selectively connected to the input terminal.Type: GrantFiled: December 2, 2009Date of Patent: August 21, 2012Assignee: Elpida Memory, Inc.Inventor: Yasuko Tonomura
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Patent number: 8223536Abstract: A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.Type: GrantFiled: September 15, 2010Date of Patent: July 17, 2012Assignee: Elpida Memory, Inc.Inventors: Yasuko Tonomura, Shuichi Tsukada
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Patent number: 8094480Abstract: A semiconductor device has a plurality of memory cells including memory elements to store information by varying resistance values of the memory elements. The semiconductor device further has a reference system circuit enables measurement of distribution of the resistance values for the plurality of memory cells.Type: GrantFiled: May 28, 2009Date of Patent: January 10, 2012Assignee: Elpida Memory, Inc.Inventor: Yasuko Tonomura
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Patent number: 8050124Abstract: A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.Type: GrantFiled: March 21, 2008Date of Patent: November 1, 2011Assignee: Elpida Memory, Inc.Inventors: Yasuko Tonomura, Satoshi Katagiri, Yukio Fuji
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Publication number: 20110063890Abstract: A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.Type: ApplicationFiled: September 15, 2010Publication date: March 17, 2011Applicant: Elpida Memory, Inc.Inventors: Yasuko Tonomura, Shuichi Tsukada
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Patent number: 7692979Abstract: In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column selecting switch, to voltage equal to or higher than hold voltage of the selected phase-change element but lower than transition voltage of the selected phase-change element in a readout cycle. The selected phase-change element is read out as a dynamic state in the case where the selected phase-change element is in a set state.Type: GrantFiled: November 21, 2007Date of Patent: April 6, 2010Assignee: Elpida Memory, Inc.Inventors: Yukio Fuji, Yasuko Tonomura
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Publication number: 20100080041Abstract: A semiconductor device includes a comparison unit for comparing a resistance value of a memory element selectively connected to an input terminal with a resistance value of a reference resistance, and a resistance reference unit capable of selecting one of a plurality of resistance values and capable of being selectively connected to the input terminal.Type: ApplicationFiled: December 2, 2009Publication date: April 1, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Yasuko Tonomura
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Publication number: 20090296452Abstract: A semiconductor device has a plurality of memory cells including memory elements to store information by varying resistance values of the memory elements. The semiconductor device further has a reference system circuit enables measurement of distribution of the resistance values for the plurality of memory cells.Type: ApplicationFiled: May 28, 2009Publication date: December 3, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Yasuko Tonomura
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Publication number: 20080247227Abstract: A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.Type: ApplicationFiled: March 21, 2008Publication date: October 9, 2008Applicant: Elpida Memory, Inc.Inventors: Yasuko TONOMURA, Satoshi KATAGIRI, Yukio Fuji
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Publication number: 20080117669Abstract: In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column selecting switch, to voltage equal to or higher than hold voltage of the selected phase-change element but lower than transition voltage of the selected phase-change element in a readout cycle. The selected phase-change element is read out as a dynamic state in the case where the selected phase-change element is in a set state.Type: ApplicationFiled: November 21, 2007Publication date: May 22, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yukio Fuji, Yasuko Tonomura