Patents by Inventor Yasukuni Inagaki

Yasukuni Inagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8149026
    Abstract: A driver circuit includes an output section; a voltage-dividing section configured to divide a first voltage at a coupling point between the output section and a termination resistor; a comparison section configured to compare a voltage difference with one of the first voltage and a second voltage, the voltage difference being a difference between the second voltage at a coupling point between the termination resistor and a transmission path and a third voltage output from the voltage-dividing section; and an adjustment section configured to adjust a voltage division ratio of the voltage-dividing section on the basis of the comparison result obtained in the comparison section.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasukuni Inagaki, Akira Mashimo
  • Publication number: 20110006812
    Abstract: A driver circuit includes an output section; a voltage-dividing section configured to divide a first voltage at a coupling point between the output section and a termination resistor; a comparison section configured to compare a voltage difference with one of the first voltage and a second voltage, the voltage difference being a difference between the second voltage at a coupling point between the termination resistor and a transmission path and a third voltage output from the voltage-dividing section; and an adjustment section configured to adjust a voltage division ratio of the voltage-dividing section on the basis of the comparison result obtained in the comparison section.
    Type: Application
    Filed: June 29, 2010
    Publication date: January 13, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasukuni INAGAKI, Akira Mashimo
  • Patent number: 5657361
    Abstract: A detector circuit for detecting abnormalities in the oscillation frequency of a clock signal, includes a counter and a comparator. The counter is supplied with a reference clock signal, and counts the number of pulses of the reference clock signal to output a signal indicative of the count value. In response to the clock signal, the counter clears the count value. The comparator compares the count value of the counter with a specified value stored in its register, and generates a detection signal indicating whether the frequency of the clock signal is within expected limits, based on the comparison result.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: August 12, 1997
    Assignee: Fujitsu Limited
    Inventors: Yasukuni Inagaki, Hitoshi Takahashi