Abstract: Systems and methods for inter-tool communication in toolbus systems in cable telemetry. The systems can include downhole equipment deployable into a wellbore via a cable, The downhole equipment can include a toolbus, a toolbus master node including a buffer, and nodes operatively coupled to the toolbus master node via the toolbus. Each of the nodes includes a buffer. Of the one or more nodes, a sending node sends a message, and a receiving node receives the message via the toolbus master node and sends a buffer full message to the toolbus master node when the buffer of the receiving node is full. The toolbus master node sends a buffer full message to the sending node and the receiving node when the buffer of the receiving node is full, and buffers the message at the toolbus master node until the receiving buffer is not full.

Abstract: Cable telemetry synchronization systems and methods. The synchronization can involve positioning downhole equipment into a wellbore via a cable operatively coupled to a surface module that can include a telemetry system master clock. The downhole equipment can include a toolbus master node and at least one slave node module having a node clock operatively coupled to the toolbus master node. The synchronization can also involve sending a frame start command to the at least one slave node module from the toolbus master node at predetermined intervals, receiving a clock value from each of the at least one slave node module, calculating a clock offset for each of the at least one slave node module, and sending an absolute clock value and the calculated clock offset for each of the at least one slave node module via a downlink synchronization command to the at least one slave node module.

Abstract: Systems and methods for inter-tool communication in toolbus systems in cable telemetry. The systems can include downhole equipment deployable into a wellbore via a cable, The downhole equipment can include a toolbus, a toolbus master node including a buffer, and nodes operatively coupled to the toolbus master node via the toolbus. Each of the nodes includes a buffer. Of the one or more nodes, a sending node sends a message, and a receiving node receives the message via the toolbus master node and sends a buffer full message to the toolbus master node when the buffer of the receiving node is full. The toolbus master node sends a buffer full message to the sending node and the receiving node when the buffer of the receiving node is full, and buffers the message at the toolbus master node until the receiving buffer is not full.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converter 12 converts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuit 8 produces trigger phase information indicating the phase relationship between the trigger signal and a reference clock. A data pattern generating circuit 10 generates parallel data bits according to the reference clock in response to the trigger signal. A data shifting circuit 11 rearranges the parallel data bits in a predetermined order to produce shifted parallel data bits in which data bit order is shifted relative to the reference clock as a function of the trigger phase information. A parallel to serial converter 16 converts the shifted parallel data bits into serial data bits.

Abstract: A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds.

Abstract: A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuit 8 produces trigger phase information indicating the phase relationship between the trigger signal and a reference clock. A data pattern generating circuit 10 generates parallel data bits according to the reference clock in response to the trigger signal. A data shifting circuit 11 rearranges the parallel data bits in a predetermined order to produce shifted parallel data bits in which data bit order is shifted relative to the reference clock as a function of the trigger phase information. A parallel to serial converter 16 converts the shifted parallel data bits into serial data bits.

Abstract: A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converter 12 converts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.

Abstract: A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds.

Abstract: A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

Abstract: A DDS type variable frequency signal generator generates a jitter free and stable output signal regardless of the address interval. If the total number of addressable memory locations of a memory storing digital data is divisible without remainder by an initial address interval, then the memory is read every initial address interval with a clock signal of a predetermined frequency. If the total number of addressable memory locations is not divisible without remainder by the initial address interval, then the address interval is modified to a value that is divisible without remainder into the total number of addressable memory locations and the clock frequency is modified in accordance with this modification of the address interval. The memory is read every modified address interval with the modified clock signal.