Patents by Inventor Yasumasa Murai

Yasumasa Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8350410
    Abstract: An uninterruptible power supply is able to switch an operation mode between an on-line operation method and an off-line operation method for a wider range of commercial power supplies.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: January 8, 2013
    Assignee: Fuji Electric Co., Ltd
    Inventor: Yasumasa Murai
  • Publication number: 20100110731
    Abstract: An uninterruptible power supply is able to switch an operation mode between an on-line operation method and an off-line operation method for a wider range of commercial power supplies.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 6, 2010
    Inventor: Yasumasa Murai
  • Patent number: 5940280
    Abstract: A battery charger converter circuit is disclosed in which a half-bridge rectifier circuit formed from two diodes, a half-bridge circuit formed from two switching elements, and a series circuit formed from two capacitors are connected at either end, respectively, thereof in parallel to each other, a boosting reactor being provided at the AC side of the half-bridge rectifier circuit; a primary circuit of the converter, including a primary coil of a high-frequency transformer, connected between a common point of connection between the switching elements and a common point of connection between the two capacitors, and a control circuit for the two switching elements; and a secondary circuit of the converter, including the secondary coil of the high-frequency transformer, a full-bridge rectifier circuit connected in parallel to the secondary coil and a smoothing capacitor; a high-frequency power generated by the primary circuit of the converter being rectified by the secondary circuit and charged into cells.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: August 17, 1999
    Assignee: Nippon Electric Industry Co., Ltd.
    Inventors: Yasumasa Murai, Hiroki Nishimura, Katsunori Sugimori
  • Patent number: 5177793
    Abstract: On recognizing first through P-th input patterns as first through P-th recognized patterns (P being greater than one) by using a plurality of reference patterns and a plurality of memorized indentifiers identifying the reference patterns, a processing circuit processes the first through the P-th input patterns into first through Q-th provisional patterns different from one another, where Q is not greater than the above-mentioned plurality. A calculating circuit calculates dissimilarity degrees had by the reference patterns relative to the first through the Q-th provisional patterns to select, with repetition allowed as selected patterns, the reference patterns which have the dissimilarity degrees less than a predetermined degree. The calculating circuit thereby selects R particular identifiers and S different identifiers from the memorized identifiers, where R plus S is not greater than P and is not less than the plurality.
    Type: Grant
    Filed: September 20, 1990
    Date of Patent: January 5, 1993
    Assignee: NEC Corporation
    Inventors: Yasumasa Murai, Toshifumi Yamauchi