Abstract: A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part which stores non-write-back information in units of address range smaller than that of the cache line, the information indicating that the write-back to the external memory is not yet performed; a mode information storing part which stores specific mode flag information which is set or reset by software in order to determine whether or not to be in a mode for not performing unnecessary write-back operation; and; and a write-back determining part which decides whether or not to write back a certain cache line before performing the DMA transfer based on the non-write-back information, when the specific mode flag is set and the write-back of the cache line is instructed.

Abstract: The present invention of a storage control apparatus which is connected to a host bus connected to a CPU (Central Processing Unit), a peripheral bus connected to at least one IP (Intellectual Property), and a system memory and controls DMA (Direct Memory Access) transfer from the IP to the system memory, having: an address map judgment section which judges whether an address given from one of the peripheral bus and the host bus indicates a memory area managed by the storage control apparatus in the system memory; a memory control section which controls data transfer to/from the system memory; a TLB (Translation Look-aside Buffer) information holding section which holds address information that indicates an area cacheable by the CPU; an address judgment section which judges on the basis of the address information held by the TLB information holding section whether the address given from one of the peripheral bus and the host bus indicates the area cacheable by the CPU; and a snoop address control section which

Abstract: A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part which stores non-write-back information in units of address range smaller than that of the cache line, the information indicating that the write-back to the external memory is not yet performed; a mode information storing part which stores specific mode flag information which is set or reset by software in order to determine whether or not to be in a mode for not performing unnecessary write-back operation; and; and a write-back determining part which decides whether or not to write back a certain cache line before performing the DMA transfer based on the non-write-back information, when the specific mode flag is set and the write-back of the cache line is instructed.