Patents by Inventor Yasumasa Nishiyama

Yasumasa Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040248536
    Abstract: A receiving circuit includes a converter 1 of which gain is switched such that the gain is decreased through a plurality of stages in response to an increase in the intensity of the received signal, for converting the received signal into an intermediate frequency signal, and a base band processing circuit 5 for switching the gain of the converter 1. The gain of the converter 1 is switched to the lower level at the output level of the converter 1 corresponding to the minimum level of the received signal input into converter 1 at which an allowable error rate is secured in the base band processing circuit 5 at the maximum gain. When the converter 1 is set up to the maximum gain mode, the level of the intermediate frequency signal is lowered by attenuation means ATT provided in the converter 1.
    Type: Application
    Filed: June 1, 2004
    Publication date: December 9, 2004
    Applicant: ALPS ELECTRIC CO., LTD.
    Inventors: Hiroyuki Sato, Yasumasa Nishiyama
  • Publication number: 20040087334
    Abstract: A multi-mode mobile communication transceiver includes a transmission circuit that outputs at least transmission signals in the AMPS mode, and a reception circuit that receives at least reception signals in the AMPS mode. A booster includes a first terminal through which signals are connected to an antenna, a power amplifier circuit connected to the first terminal, and a reception-signal sending circuit connected to the first terminal. When the booster is connected with the multi-mode mobile communication transceiver, the transmission circuit is connected in series with the power amplifier circuit, and the reception-signal sending circuit is connected in series with the reception circuit.
    Type: Application
    Filed: October 21, 2003
    Publication date: May 6, 2004
    Applicant: Alps Electric Co., Ltd.
    Inventor: Yasumasa Nishiyama
  • Patent number: 6445166
    Abstract: A power supply circuit includes a power supply voltage input terminal; a load voltage output terminal; a voltage stabilizer circuit having a first voltage input terminal and a first voltage output terminal, which stabilizes a voltage input to the first voltage input terminal and which outputs a rated voltage from the first voltage output terminal; and a ripple reducing circuit having a second voltage input terminal and a second voltage output terminal, which reduces ripple in a voltage input to the second voltage input terminal and outputs from the second voltage output terminal. The first voltage input terminal and the second voltage input terminal are connected to the power supply voltage input terminal, while the first voltage output terminal and the second voltage output terminal are connected to the load voltage output terminal.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: September 3, 2002
    Assignee: Alps Electric Co., Ltd.
    Inventor: Yasumasa Nishiyama
  • Publication number: 20020017957
    Abstract: An oscillator includes an oscillation transistor; a power supply resistor for supplying a bias voltage to the base of the oscillation transistor; and an NPN transistor whose collector is connected to the power supply and whose emitter is connected to the power supply resistor. A capacitor is connected between the base of the NPN transistor and the ground. A resistor is connected between the power supply and the base of the NPN transistor.
    Type: Application
    Filed: September 28, 2001
    Publication date: February 14, 2002
    Applicant: Alps Electric Co., Ltd.
    Inventor: Yasumasa Nishiyama
  • Publication number: 20010015637
    Abstract: A power supply circuit includes a power supply voltage input terminal; a load voltage output terminal; a voltage stabilizer circuit having a first voltage input terminal and a first voltage output terminal, which stabilizes a voltage input to the first voltage input terminal and which outputs a rated voltage from the first voltage output terminal; and a ripple reducing circuit having a second voltage input terminal and a second voltage output terminal, which reduces ripple in a voltage input to the second voltage input terminal and outputs from the second voltage output terminal. The first voltage input terminal and the second voltage input terminal are connected to the power supply voltage input terminal, while the first voltage output terminal and the second voltage output terminal are connected to the load voltage output terminal.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 23, 2001
    Applicant: Alps Electric Co., Ltd.
    Inventor: Yasumasa Nishiyama