Abstract: A vector processing apparatus includes a main memory, an instruction issuing section which issues instructions, an overtaking control circuit which outputs the instructions received from the instruction issuing section to an instruction executing section in an order based on whether each of a first and second instructions belongs to a first specific instruction group, whether each of the first and second instructions belongs to a second specific instruction group in the first specific instruction group, whether a fourth instruction belongs to a fourth specific instruction group, whether a third instruction belongs to a third specific instruction group, and whether an address area of the main memory relating to the third instruction and an address area of the main memory relating to each of the first and second instructions do not overlap, and the instruction executing section executes the instructions received from the overtaking control circuit.

Abstract: An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with access patterns. A hit determination unit determines the hit way when a cache access hit occurs. A way number increase/decrease determination unit manages, for each of the ways that are in operation, the order from the way for which the time of use is most recent to the way for which the time of use is oldest. The way number increase/decrease determination unit then finds the rank of the hit ways that have been obtained in the hit determination unit and counts the number of hits for each rank in the order. The way number increase/decrease determination unit further determines increase or decrease of the number of operated ways based on the access pattern that is indicated by the relation of the number of hits to each rank in the order.

Abstract: An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with access patterns. A hit determination unit determines the hit way when a cache access hit occurs. A way number increase/decrease determination unit manages, for each of the ways that are in operation, the order from the way for which the time of use is most recent to the way for which the time of use is oldest. The way number increase/decrease determination unit then finds the rank of the hit ways that have been obtained in the hit determination unit and counts the number of hits for each rank in the order. The way number increase/decrease determination unit further determines increase or decrease of the number of operated ways based on the access pattern that is indicated by the relation of the number of hits to each rank in the order.

Abstract: A vector processing apparatus includes a main memory, an instruction issuing section, an overtaking control circuit and an instruction executing section. The instruction issuing section sequentially issues instructions. A first instruction of the instructions is issued, and then a second instruction thereof is issued, a fourth instruction thereof is issued before a third instruction thereof which is issued after the second instruction.