Patents by Inventor Yasumasa Sawada

Yasumasa Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240093756
    Abstract: An anti-vibration device is secured to a vibration source and a vibration transmission portion to inhibit transmission of vibration, and includes a first elastically deformed portion, a second elastically deformed portion and a third elastically deformed portion. The first elastically deformed portion is a plate having a thickness in a first thickness direction and vibrates in the first thickness direction to configure a path for the vibration to be transmitted from the vibration source to the vibration transmission portion. The second elastically deformed portion is a plate having a thickness in a second thickness direction intersecting the first thickness direction and vibrates in the second thickness direction to configure the path. The third elastically deformed portion is a plate having a thickness in a third thickness direction intersecting the first thickness direction and the second thickness direction and vibrates in the third thickness direction to configure the path.
    Type: Application
    Filed: May 31, 2023
    Publication date: March 21, 2024
    Applicant: DENSO CORPORATION
    Inventors: Kazuhiro HAYASHI, Yasumasa YAMAZAKI, Motohiko UEDA, Yoshikatsu SAWADA, Takaya MORISHITA
  • Patent number: 6376295
    Abstract: There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: April 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyomi Naruke, Minoru Kurata, Yuuichi Tatsumi, Yasumasa Sawada