Abstract: A master-slice type semiconductor chip in the form of a PGA package has a plurality of external pins arranged in a plurality of rows. The external pins of at least the outermost row are electrically connected to an input cell on the semiconductor chip, while the external pins of at least the innermost row is connected to an input/output cell provided on the semiconductor chip. With this arrangement, the wires in the package connected to the input/output cell can have smaller lengths than the wires connected to the input cell, so that crosstalk noises produced by output signals can be reduced.

Abstract: An ECL latch circuit includes a logic section and has a reset or set function. The logic section includes a first to seventh transistors. The third transistor has a collector connected to the collector of the first transistor, and a base for receiving a first reference potential or the collector potential of the second transistor through an emitter follower section. The fourth transistor has a collector connected to the collector of the second transistor, a base for receiving a collector potential of the first transistor through an emitter follower section or receiving a first reference potential, and an emitter connected to the emitter of the third transistor. The fifth transistor has a collector connected to the collector of the second or first transistor, a base for receiving a reset or set signal, and an emitter connected to the emitter of the third transistor.

Abstract: A master-slice type emitter coupled logic circuit includes a first and a second inverter circuit and a two-input AND circuit which receives output signals from the first and second inverter circuits. Each of the first and second inverter circuits has an emitter follower circuit having a level shift circuit and an emitter follower transistor whose collector is connected to a higher potential power source, whose base receives a logic signal, and whose emitter is coupled to a lower potential power source. The emitter of the emitter follower transistor in the first inverter circuit is coupled to the lower potential power source through only a load resistor, whereas that in the second inverter circuit is coupled to the lower potential power source through the level shift circuit and the load resistor. The level shift circuit is formed by at least one diode whose anode is to be connected with the emitter of the emitter follower transistor and whose cathode is to be connected with one end of the load resistor.

Abstract: A collector-dotted current-mode logic circuit which includes a plurality of current-mode logic circuits each containing a first and a second transistors, where the collectors of the first transists and the collectors of the second transistors are respectively connected. A load consisting only of a resistor is connected to the collectors of the first transistors. A load is also connected to the collectors of the second transistors. When the signal level at the collectors of the second transistors is "H", the current supplied by one of the constant current sources that supply currents to the resistor load is bypassed by way of a bypass circuit. As a result, the "L" level at the collector of the first transistor where logic is output, is so controlled as to maintain its constancy for any condition of the logic signal input to this current-mode logic circuit.

Abstract: A semiconductor integrated circuit comprises a bus line having a first node from which a power source voltage is supplied to the bus line and second nodes, constant-voltage circuits connected to the second nodes of the bus line, respectively, and a plurality of constant-current sources arranged between the constant-voltage circuits. The fist node is positioned at a middle portion between the second nodes.

Abstract: A constant current source circuit comprises a first FET connected to a first voltage line at its drain region and to a second voltage line through an impedance circuit at its source region and gate in common; a second FET connected to the first voltage line at its drain region and its source region and gate being connected to each other; a third FET connected to the source region of the second FET at its drain region, to the second voltage line at its source region and to the source region of the first FET at its gate; and a fourt FET connected to a current output node of the circuit at its drain region, to the second voltage line at its source region and to the source region of the second FET at its gate. Every FET is operated at the saturation state.

Abstract: A constant current source circuit, in which first and second FET's are formed, is disclosed. The first FET has a source-drain path connected between power voltage lines and a gate connected to one of the power voltage lines with the source in common. The second FET is connected at its drain to a current output node of the constant current source circuit for supplying a constant current to a circuit coupled to the current output node, and at its gate to the drain of the first FET.

Abstract: There is disclosed a semiconductor device comprising a plurality of lower level interconnections having first, second and third lower level interconnections, an upper level interconnection connected to the first and second lower level interconnections and extending over the third lower level interconnection in spacing relationship, and at least one pier formed on a central portion of the upper surface of one of the first and second lower level interconnections, and the pier has a width less than that of aforesaid one of the first and second lower level interconnections and is covered in its entire surface with a film formed of the same material as of the upper level interconnection, so that a force applied for wafer separation is partially supported by the pier.