Patents by Inventor Yasumitsu K. Orii

Yasumitsu K. Orii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941230
    Abstract: The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keiji Matsumoto, Keishi Okamoto, Yasumitsu K. Orii, Kazushige Toriyama
  • Publication number: 20170194277
    Abstract: The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Keji Matsumodo, Keishi Okamoto, Yasumitsu K. Orii, Kazushige Toriyama
  • Patent number: 9520375
    Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Hiroyuki Mori, Yasumitsu K. Orii, Kazushige Toriyama, Shintaro Yamamichi
  • Publication number: 20160322319
    Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Inventors: Toyohiro Aoki, Hiroyuki Mori, Yasumitsu K. Orii, Kazushige Toriyama, Shintaro Yamamichi