Abstract: A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.

Abstract: A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.

Abstract: A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.

Abstract: A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Abstract: Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Abstract: A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.

Abstract: A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.

Abstract: The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.

Abstract: An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.

Abstract: In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.

Abstract: A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

Abstract: To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.

Abstract: In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells.