Abstract: A static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring which are provided to extend in a direction of a word line; and inverters provided between the power supply wiring and the ground wiring and cross-connected to each other. The dummy memory cell includes first and second wirings respectively corresponding to the power supply wiring and the ground wiring and extending in the direction of the word line; and two sets of a dummy load circuit and a dummy drive transistor, wherein the two sets are connected with the first and second wirings, which are biased to prevent leakage current from flowing.

Abstract: A semiconductor device comprises a decoupling capacitance in which a P-type MOS capacitor C1 is connected in series with an N-type MOS capacitor C2 between VDD and GND. The source and drain 2b of the P-type MOS capacitor C1 are connected to VDD. The source and drain 2a of the N-type MOS capacitor C2 are connected to GND. The gate electrode 5a of the P-type MOS capacitor C1 is connected to the gate electrode 5b of the N-type MOS capacitor C2. VDD is connected to the N-well region 1b of the channel of the P-type MOS capacitor C1, and GND is connected to the P-well region 1a of the channel of the N-type MOS capacitor C2. Reliability of decoupling capacitance is improved, making it possible to place elements efficiently.

Abstract: A static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring which are provided to extend in a direction of a word line; and inverters provided between the power supply wiring and the ground wiring and cross-connected to each other. The dummy memory cell includes first and second wirings respectively corresponding to the power supply wiring and the ground wiring and extending in the direction of the word line; and two sets of a dummy load circuit and a dummy drive transistor, wherein the two sets are connected with the first and second wirings, which are biased to prevent leakage current from flowing.

Abstract: A transistor circuit for marking is provided at a semiconductor chip. This circuit includes a P-type MOS transistor and an N-type MOS transistor connected in series between a power supply pad and a ground pad, the first inverter connected to a test signal terminal and having an output terminal connected to a drain of the N-type MOS transistor and the second inverter into which an output signal of the first inverter is inputted and an output terminal of which is connected to a drain of the P-type MOS transistor. If a chip functional test is performed and the chip is determined as a defective, then a signal inputted to the terminal is turned into a high level to cause latch-up to occur to the marking transistor circuit and the transistor is damaged, whereby the marking transistor circuit can be visually identified. As a result, it is possible to ensure identify a defective chip and to prevent adversely affecting adjacent chips.