Abstract: To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.

Abstract: To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.

Abstract: A mounting structure which reduces the mechanical stress added to a low-? material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-? layer formed on top a semiconductor substrate; an electrode layer formed on the low-? layer; a protective layer formed the low-? layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer.

Abstract: A mounting structure which reduces the mechanical stress added to a low-? material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-? layer formed on top a semiconductor substrate; an electrode layer formed on the low-? layer; a protective layer formed the low-? layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer.

Abstract: Problem To improve the electromigration (EM) resistance of a solder joint. Solution The present invention provides a unique structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint, and a unique method of forming this structure. More specifically, in this unique structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.

Abstract: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a substrate is set to be located at a predetermined height h from a surface of a base plate. Thereafter, through machining the surface of the semiconductor component which is adjusted to be located at the predetermined height, it is possible to make the thickness of the semiconductor component on the substrate equal to a predetermined thickness.

Abstract: A method for mounting a semiconductor part on a circuit substrate is provided, which includes preparing the semiconductor part having a surface thereof provided with a plurality of stud-bumps, preparing a solder substrate having a surface thereof on which solid-solders corresponding to respective ones of the plurality of stud-bumps are arranged, preparing the circuit substrate having a surface thereof provided with connecting pads corresponding to respective ones of the plurality of stud-bumps, attaching the corresponding solid-solders on the solder substrate to respective tip ends of the plurality of stud bumps, separating the solid-solders attached to the tip ends of the stud-bumps from the solder substrate, contacting the solid-solder attached to respective ones of the tip ends of the stud-bumps with the corresponding connecting pads, and heating the solid-solders contacted with the corresponding connecting pads thereby establishing solder connection between respective ones of the stud-bumps and the corres

Abstract: A multilayer circuit board is provided that includes at least two insulating layers each sandwiched by circuit layers, thus having at least one internal circuit layer sandwiched by the at least two insulating layers. Via holes are formed in one or more of the insulating layers at the same pitch as bump electrodes of an integrated circuit chip, which permit insertion of the bump electrodes of an integrated circuit chip into the via holes of the multilayer circuit board. Metal films formed within the via holes are electrically connected to at least one of the circuit layers. An internal capacitor may be formed in a predetermined area of an insulating layer and predetermined areas of circuit layers which sandwich the predetermined area of the insulating layer and are opposed to each other. An internal resistor may be formed in an inner circuit layer.

Abstract: A method for mounting a semiconductor part on a circuit substrate is provided, which includes preparing the semiconductor part having a surface thereof provided with a plurality of stud-bumps, preparing a solder substrate having a surface thereof on which solid-solders corresponding to respective ones of the plurality of stud-bumps are arranged, preparing the circuit substrate having a surface thereof provided with connecting pads corresponding to respective ones of the plurality of stud-bumps, attaching the corresponding solid-solders on the solder substrate to respective tip ends of the plurality of stud bumps, separating the solid-solders attached to the tip ends of the stud-bumps from the solder substrate, contacting the solid-solder attached to respective ones of the tip ends of the stud-bumps with the corresponding connecting pads, and heating the solid-solders contacted with the corresponding connecting pads thereby establishing solder connection between respective ones of the stud-bumps and the corres

Abstract: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a substrate is set to be located at a predetermined height h from a surface of a base plate. Thereafter, through machining the surface of the semiconductor component which is adjusted to be located at the predetermined height, it is possible to make the thickness of the semiconductor component on the substrate equal to a predetermined thickness.

Abstract: A multilayer circuit board is provided that includes at least two insulating layers each sandwiched by circuit layers, thus having at least one internal circuit layer sandwiched by the at least two insulating layers. Via holes are formed in one or more of the insulating layers at the same pitch as bump electrodes of an integrated circuit chip, which permit insertion of the bump electrodes of an integrated circuit chip into the via holes of the multilayer circuit board. Metal films formed within the via holes are electrically connected to at least one of the circuit layers. An internal capacitor may be formed in a predetermined area of an insulating layer and predetermined areas of circuit layers which sandwich the predetermined area of the insulating layer and are opposed to each other. An internal resistor may be formed in an inner circuit layer.

Abstract: Methods and apparatuses to perform soldering while the chip is held by a head under melted solder condition are disclosed. Solder bumps 3 are formed on the chip 1, and they are opposite to terminals 11 on a mounting board 10. Furthermore, a heating block 21 is located at the back of the chip, and it raises the temperature of the solder bumps 3 on the chip 1 to a melting point by heating the chip back by conduction. Preferably, another heating block 22 is located at the back of the mounting board 10. Soldering is performed by bringing the solder bumps 3 into contact with the terminals 11 while the solder is melted.