Patents by Inventor Yasumoto Komiya

Yasumoto Komiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaging substrate and semiconductor device
    Publication number: 20020011662
    Abstract: A low-impedance connection is provided between an LSI and a capacitor (for example, existing internal capacitance of an electronic part) in the power supply path to limit power supply noise, which can be a factor in high-speed logic circuit malfunctions. For example, a packaging substrate and a semiconductor device using the same are provided which reduce power supply path inductance, which is a major factor in impedance.
    Type: Application
    Filed: April 23, 2001
    Publication date: January 31, 2002
    Inventors: Yasumoto Komiya, Takashi Suga, Yoshihiko Hayashi