Abstract: A Unified Memory Architecture (UMA) using intelligent media memory provides an improved way of solving the granularity and memory bandwidth problems in the electronic computer memory system. A specially designed memory chip is attached to an existing attachment point of the system by integrating the bus interface on the memory chip. The memory chip additionally integrates on-chip data-intensive computation functions with the dynamic random access memory (DRAM) macros. Two system attachment points for the new integrated DRAM and logic chip are disclosed; the first using the local central processing unit (CPU) bus interface, and the second using a combination of the main memory bus and an alternative system bus such as a Peripheral Component Interconnect (PCI) bus.

Abstract: A memory cell comprises at least three conducting layers (20) spaced apart by insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunneling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunneling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made.

Abstract: A dynamic random access memory (DRAM) of 2/3 VDD precharge scheme is disclosed. A latch driving circuit controls the voltage of the common node of a sense latch so as to limit the downward voltage swing of bitlines to 1/3 VDD, a low level restore voltage. The sense latch is coupled to a pair of I/O data lines through PMOS FET column switches. This invention provides high speed memory operation and reduces power consumption.