Abstract: A guide wire that is durable against twisting stress includes a first shaft and a second shaft having a distal end joined to a proximal end of the first shaft. The second shaft is formed of a material exhibiting an elastic modulus higher than that of a material forming the first shaft. The second shaft includes a variable hardness portion including a first portion having a hardness that gradually decreases from a distal end to a proximal end of the first portion, and a second portion arranged proximally of the first portion, and exhibiting a hardness lower than the hardness of the distal end of the first portion. The length of the variable hardness portion in the axial direction of the guide wire is longer than the diameter of the second shaft.

Abstract: A semiconductor memory test apparatus has a log data generating unit for generating log data indicating a test result of a device under test based on output data from the device under test corresponding to a predetermined test pattern; and a log data storing unit for writing the generated log data sequentially and reading the stored log data sequentially. The log data storing unit, having a dual port structure, includes a memory portion, an input port and an output port.

Abstract: A semiconductor chip inspection supporting apparatus includes a data processing unit. To the data processing unit, an image data is supplied. The image data indicates a layout of a plurality of normal chips and a plurality of abnormal chip on a semiconductor wafer. The data processing unit includes a data processing unit and a search processing portion. The generation portion generates a connection propriety data indicating prohibition of each of the plurality of normal chips from being connected to adjacent one of the plurality of abnormal chips based on the image data. The search processing portion searches for a chip to be paired with the each of plurality of the normal chips for execution of paired measurement, based on the image data and the connection propriety data. The data processing unit outputs the search result.

Abstract: A semiconductor chip inspection supporting apparatus includes a data processing unit. To the data processing unit, an image data is supplied. The image data indicates a layout of a plurality of normal chips and a plurality of abnormal chip on a semiconductor wafer. The data processing unit includes a data processing unit and a search processing portion. The generation portion generates a connection propriety data indicating prohibition of each of the plurality of normal chips from being connected to adjacent one of the plurality of abnormal chips based on the image data. The search processing portion searches for a chip to be paired with the each of plurality of the normal chips for execution of paired measurement, based on the image data and the connection propriety data. The data processing unit outputs the search result.

Abstract: A semiconductor memory test apparatus for testing a device under test using a predetermined test pattern comprises log data generating means for generating log data indicating a test result of the device under test based on output data from the device under test corresponding to the test pattern; and log data storing means for writing the generated log data sequentially and reading the stored log data in accordance with a read request. The log data storing means controls a write and read operation of the log data asynchronously and independently, and the log data can be repeatedly read out during execution of a test by the read request.

Abstract: A disenabling circuit upon a power-on event comprises a level detecting circuit provided with a series combination of plural p-channel type load transistors and at least one n-channel type shifting transistor coupled between a positive power supplying line and a ground terminal, and a complementary inverter circuit coupled at an input node thereof to the output node of the level detecting circuit and having an output node where a disenabling signal of active high level is produced. The shifting transistor is responsive to the voltage level at the output node of the complementary inverter circuit, so that no conduction path takes place in the level shifting circuit after the disenabling signal recovers from the active level to the inactive low level.