Abstract: Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read/write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read/write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.

Abstract: Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read/write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read/write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells having a DRAM cell structure and is treated as a SRAM memory device without controlling the data refreshing cycle for the memory cells. The refreshing cycle is separated into a read operation and a write operation, which sandwich therebetween a read/write operation for the input address of the memory cell. The data read in the refreshing cycle is saved in a refreshing sense amplifier during the read/write operation and stored in the memory cell after the read/write operation.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells having a DRAM cell structure and is treated as a SRAM memory device without controlling the data refreshing cycle for the memory cells. The refreshing cycle is separated into a read operation and a write operation, which sandwich therebetween a read/write operation for the input address of the memory cell. The data read in the refreshing cycle is saved in a refreshing sense amplifier during the read/write operation and stored in the memory cell after the read/write operation.

Abstract: A method and apparatus for facilitating communications in a hierarchical network between slave servers communicating in a first data format and slave servers communicating in a second data format. A second version of network software which coexists with an existing first version of network software is installed in a master server. The first version of the network software processes data in a first format and the second version of the network software processes data in a second format different from the first format. The master server is provided with a first converting means for converting the first format data to the second format data when a first predetermined event is detected, and a second converting means for converting the second format data to the first format data when a second predetermined event is detected.

Abstract: A pipe-line processing/burst read SRAM generates an echo clock signal concurrently with the output timing of read data. The memory cell array includes a pair of memory cells storing a high level data and a low level data. The echo clock signal is generated by reading data from the pair of memory cells and alternately outputting the read data. The timing of the echo clock signal is concurrent with the output timing of read data from a data output section which reads data from a memory cell specified by a read address.

Abstract: In a semiconductor memory device having a burst function, a memory circuit inputs and outputs information corresponding to an external input signal in synchronization with an internal clock signal. A burst operation control circuit receives an external reference clock signal and an enable signal for switching a burst operation mode and a stand-by mode, so as to suspend supplying of the external input signal in the burst operation mode and suspend generation of the first internal clock signal in the stand-by mode.