Abstract: A calculating apparatus performs FFT calculation or IFFT calculation on input data and then outputs the calculated data. An input buffer memory temporarily stores the input data and outputs it to a memory. An output buffer memory temporarily stores the final data of the calculating apparatus and then outputs it to an external source. The input buffer memory or the output buffer memory is provided with an address generating circuit. The address generating circuit sets the write addresses or the read addresses of the data to be stored in either buffer memory in a predetermined order. Thus, the frequency domain of the data in the calculating apparatus is converted without requiring the use of an external circuit.

Abstract: Butterfly calculations of a cardinal number of four and butterfly calculations of a cardinal number of two are performed by using the same circuitry. When butterfly calculations of a cardinal number of two are performed, predetermined lines in the circuitry are removed by using selectors. Moreover, the multiplication factors of the signal lines which join predetermined complex multiplication circuits with predetermined complex addition circuits are changed from −j to −1, from −1 to 1, from −1 to 1, and from −j to −1. As a result, a pair of butterfly calculating circuit systems (A and B) are formed. On the other hand, when calculations of a cardinal number of four are performed, all the signal lines in the circuitry are connected, and the predetermined multiplication factors of the respective paths are set. As a consequence, a single butterfly calculating circuit system having a cardinal number of four is formed.

Abstract: A computation apparatus such as a Fast Fourier Transform (FFT) apparatus which processes ordered sets of data in a computation unit (4, 24) operating according to a high-speed clock includes an input buffer (1, 21) arranged to accept data in synchronism with a relatively low-speed clock, and an output buffer (6, 26) arranged to discharge the data in synchronism with the low-speed clock. The apparatus includes an internal memory (3, 23) as well as means such as selectors (2, 22) and (5, 25) for transferring data in synchronism with the high-speed clock from the input buffer to the computation unit or the memory; between the computation unit and the memory; and from the computation unit or the memory to the output buffer. The transferring means is arranged to reorder the data, preferably in reverse-digit sequence, during transfer from the input buffer or during transfer to the output buffer. This avoids the need for a separate reordering memory at the input end or output end of the device.

Abstract: In order to carry out FFT operations at a high speed, a configuration is adopted where, while a FFT (fast Fourier transform) operation or inverse FFT (inverse fast Fourier transform) operation is being carried out by performing a prescribed number of butterfly operations with the output of a butterfly operator being fed-back to the input of the butterfly operator, at least one of: a first storage part for storing data inputted to the butterfly operator; a second storage part for temporarily storing data outputted from the butterfly operator and feeding-back read-out data to an input of the butterfly operator; and a third storage part, for storing data that has undergone a butterfly operation a prescribed number of times, has a storage part, with the storage part comprising a plurality of divided storage parts.