Patents by Inventor Yasunari Tagami

Yasunari Tagami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6114744
    Abstract: A lead electrode is formed to expose an active base region. A lead electrode for an emitter electrode is formed on the lead electrode in an emitter region, through an insulating film. The insulating film on the lead electrode is then etched to form a contact hole. After that, the emitter contact hole is formed to expose the lead electrode. Also, a silicon nitride film SN is interposed between the lead electrode and insulating film and between the lead electrode and LOCOS oxide film each to decrease resistance of the lead electrodes.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: September 5, 2000
    Assignee: Sanyo Electric Company
    Inventors: Masayuki Kawaguchi, Yasunari Tagami, Hirotsugu Hata, Akira Hatsugai
  • Patent number: 6110772
    Abstract: A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: August 29, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tadayoshi Takada, Tsuyoshi Takahashi, Yasunari Tagami, Hirotsugu Hata, Satoru Kaneko
  • Patent number: 5719066
    Abstract: A lower layer diffusion layer of a metal-insulator-semiconductor-type (MIS-type) condenser is formed by implanting and diffusing phosphorus into an upper portion of an epitaxial layer formed on a semiconductor substrate. Thereafter, a silicon nitride film functioning as a dielectric film of the MIS type condenser is formed on the lower layer diffusion layer, and a poly-silicon film functioning as a protective film for the silicon nitride film is formed on the silicon nitride film in succession to the formation of the silicon nitride film without performing any etching operation. The formation of the silicon nitride film and the poly-silicon film is performed according to a vacuum chemical vapor deposition in the same chamber to prevent the silicon nitride film from being exposed to oxygen. Thereafter, the silicon nitride film and the poly-silicon film are baked to form an oxidized film surrounding the silicon nitride film and the poly-silicon film.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: February 17, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshiaki Sano, Toshimasa Sadakata, Yasunari Tagami, Yasuo Oishibashi