Abstract: A muting circuit of the present invention includes: an input terminal that receives a control signal for allowing switching between ON and OFF of a mute operation; and a muting transistor connected to the input terminal and an output terminal of the amplifier. The muting transistor is a MOS transistor, and a gate is connected to the input terminal, a drain is connected to the output terminal of the amplifier, and a source is grounded. Consequently, a shot noise due to a DC difference caused when a mute state is switched between ON and OFF can be suppressed.

Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.

Abstract: A muting circuit of the present invention includes: an input terminal that receives a control signal for allowing switching between ON and OFF of a mute operation; and a muting transistor connected to the input terminal and an output terminal of the amplifier. The muting transistor is a MOS transistor, and a gate is connected to the input terminal, a drain is connected to the output terminal of the amplifier, and a source is grounded. Consequently, a shot noise due to a DC difference caused when a mute state is switched between ON and OFF can be suppressed.

Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.