Patents by Inventor Yasunobu Kato

Yasunobu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6014731
    Abstract: In a storage disk control apparatus, a load of a computer caused by transferring data is reduced, and a waiting time until a data transfer operation is commenced is shortened. In the disk control method for controlling a disk apparatus including a disk having a plurality of storage regions for storing data therein by way of an external apparatus external addresses produced from the external apparatus are related to internal addresses indicative of positions of the storage regions the external addresses are converted into the internal addresses related thereto, and the disk is accessed based on the internal addresses.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: January 11, 2000
    Assignee: Sony Corporation
    Inventors: Takashi Totsuka, Yasunobu Kato, Noboru Oya, Hiroyuki Shioya
  • Patent number: 5914916
    Abstract: A method and apparatus for controlling the access to a recording disk which determines a skew so that a rotational delay time at an average distance of movement when a head accesses the recording disk is minimized. The methods and apparatus determine the position of a data block on the recording disk based on at least the determined skew, schedules an order of a plurality of input disk access requests so that an amount of movement of the head becomes small at the time of access with respect to the recording disk by the head, and the head accesses the recording disk based on the result of the scheduling.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: June 22, 1999
    Assignee: Sony Corporation
    Inventors: Takashi Totsuka, Yasunobu Kato, Noboru Oya, Hiroyuki Shioya
  • Patent number: 5774498
    Abstract: A reordering device 1.sub.-- 1 rearranges the segments of each block of time series data comprised of a plurality of blocks in block units. A selecting device 2.sub.-- 1 selects from among a plurality of time series data S1.sub.-- 1 to 1.sub.-- 4 rearranged by the reordering device 1 by switching in accordance with the speed and transmits the corresponding segments of the selected time series data sequentially to the reordering device 3.sub.-- 1 etc. as the streams S2.sub.-- 1 etc. The repeat reordering device 3.sub.-- 1 rearranges the segments contained in the stream S2.sub.-- 1 in units of blocks so as to restore the original order and transmits this rearranged time series data.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: June 30, 1998
    Assignee: Sony Corporation
    Inventors: Noboru Oya, Takashi Totsuka, Yasunobu Kato, Hiroyuki Shioya
  • Patent number: 5708632
    Abstract: A method and apparatus for controlling the access to a recording disk which determines a skew so that a rotational delay time at an average distance of movement when a head accesses the recording disk is minimized. The methods and apparatus determine the position of a data block on the recording disk based on at least the determined skew, schedules an order of a plurality of input disk access requests so that an amount of movement of the head becomes small at the time of access with respect to the recording disk by the head, and the head accesses the recording disk based on the result of the scheduling.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: January 13, 1998
    Assignee: Sony Corporation
    Inventors: Takashi Totsuka, Yasunobu Kato, Noboru Oya, Hiroyuki Shioya
  • Patent number: 5524264
    Abstract: A parallel arithmetic-logical processing device in which arithmetic-logical processing is shared among and executed in a parallel fashion by a plurality of processing elements. The device includes a large-capacity serial access memory for continuous reading/writing of large-scale data, a small-capacity serial access memory for continuous reading/writing of small-scale data and a high-speed general-purpose random access memory for random writing/readout of small-scale data. A central processing unit (CPU) causes the memories to be used or not used depending on the scale of the arithmetic-logical processing. Since the serial access memory executes continuous data writing and reading, high-speed access may be achieved, so that it can be manufactured inexpensively with a large storage capacity. Consequently, the processing speed in the CPU may be increased, while the parallel arithmetic-logical processing device may be manufactured inexpensively.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: June 4, 1996
    Assignee: Sony Corporation
    Inventors: Norihisa Shirota, Yasunobu Kato, Noboru Oya