Patents by Inventor Yasunobu Nakamura

Yasunobu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090008789
    Abstract: A method of manufacturing a micro tunnel-junction circuit capable of remarkably relieving the limitation of a circuit pattern to be manufactured and remarkably relieving the limitation of a metallic material to be used. In the method, a three-layer structure is formed by laminating a first metal, an insulator, and a second metal on a substrate in this order, a narrow wall part is formed by cutting the three-layer structure in the depth direction by using a converging ion beam, at least one laterally passed through-hole is formed in the wall part by using the converging ion beam, and at least one recessed portion positioned adjacent to the hole is formed by cutting the upper surface of the wall part in the depth direction. The hole is a through-hole starting at the position of the head of the second metal to the position of the head of the substrate and the recessed part is formed to be recessed from the upper surface of the wall part into the first metal.
    Type: Application
    Filed: August 3, 2004
    Publication date: January 8, 2009
    Applicants: Riken, NEC Corporation
    Inventors: Michio Watanabe, Yasunobu Nakamura
  • Patent number: 7145170
    Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 5, 2006
    Assignees: NEC Corporation, Riken
    Inventors: Tsuyoshi Yamamoto, Yasunobu Nakamura, Jaw-Shen Tsai
  • Publication number: 20050062072
    Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.
    Type: Application
    Filed: August 4, 2004
    Publication date: March 24, 2005
    Applicants: NEC Corporation, Riken
    Inventors: Tsuyoshi Yamamoto, Yasunobu Nakamura, Jaw-Shen Tsai
  • Patent number: 6635697
    Abstract: The present invention provides a flame-retardant which is not only excellent in flame-retarding property but also devoid of lowering moisture-resisting property specially in the course of molding of a resin so that the flame-retardant has little limitation for the molding method, the molding conditions and the intended use thereof. What is characterized is a flame-retardant comprising (a) an aliphatic amine salt of a phosphoric ester with 2-25 carbon atoms in the ester moiety thereof having a melting point of at least 100° C. but not more than a molding temperature of a thermoplastic resin and (b) a salt of phosphoric and/or polyphosphoric acid, the proportion of the component (a) to the component (b), i.e. (a)/(b) being 1/2-5/1 by weight ratio.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: October 21, 2003
    Assignee: Idemitsu Petrochemical Co., Ltd.
    Inventors: Tetsuo Kuwaki, Yasunobu Nakamura, Yasuhiro Muneuchi
  • Patent number: 6507509
    Abstract: High device reliability, a reduction in power consumption, and a high operation speed are achieved. When a predetermined bias voltage is applied between a source 1 and a drain 2 to change a gate voltage, a current discretely flows between the source 1 and the drain 2 in accordance with quantized electrostatic energy levels in an island electrode 3. The switching ON/OFF of the current between the source 1 and the drain 2 in this case is enabled by applying ½-electron charge to a gate. When the gate voltage induces polarization in a ferroelectric layer 6, its electric field is applied to the island electrode 3. The current between the source 1 and the drain 2 in this case can be measured with high sensitivity. Charge holding is carried out by the polarization in the ferroelectric layer 6, and stored data can be held even if power supply is cut off.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: January 14, 2003
    Assignees: Japan Science and Technology Corporation, NEC Corporation
    Inventors: Youichi Ohtsuka, Junichi Sone, Jaw-Shen Tsai, Takanari Yasui, Yasunobu Nakamura
  • Publication number: 20020040083
    Abstract: The present invention provides a flame-retardant which is not only excellent in flame-retarding property but also devoid of lowering moisture-resisting property specially in the course of molding of a resin so that the flame-retardant has little limitation for the molding method, the molding conditions and the intended use thereof. What is characterized is a flame-retardant comprising (a) an aliphatic amine salt of a phosphoric ester with 2-25 carbon atoms in the ester moiety thereof having a melting point of at least 100° C. but not more than a molding temperature of a thermoplastic resin and (b) a salt of phosphoric and/or polyphosphoric acid, the proportion of the component (a) to the component (b), i.e. (a)/(b) being ½-{fraction (5/1)} by weight ratio.
    Type: Application
    Filed: January 24, 2001
    Publication date: April 4, 2002
    Inventors: Tetsuo Kuwaki, Yasunobu Nakamura, Yasuhiro Muneuchi
  • Patent number: D258057
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: January 27, 1981
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuo Takanaga, Yasunobu Nakamura, Kazuhiko Nagata, Kenji Nishiyama