Abstract: To provide a thin-film capacitor capable of preventing the degradation of electrical characteristics caused by direct contact between an adhesion layer of a terminal electrode and a dielectric layer, to increase the reliability.

Abstract: A dielectric device comprises a substrate made of a metal and an oxide dielectric layer mounted on a surface of the substrate. The surface of the substrate has metal oxide regions distributed like islands, while the oxide dielectric layer is in close contact with the substrate through the metal oxide regions. Since adhesion is higher in an area where the substrate and the oxide dielectric layer are in close contact with each other through the metal oxide regions distributed like islands on the surface of the substrate, the adhesion between the substrate and oxide dielectric layer in the dielectric device is enhanced. As compared with a case where a rough surface is formed on a metal foil, the metal oxide region and the substrate are inhibited from forming a rough surface, whereby leakage characteristics can be kept from being deteriorated by the rough surface.

Abstract: A method of manufacturing a thin film capacitor, having: a base electrode; dielectric layers consecutively deposited on the base electrode; an internal electrode deposited between the dielectric layers; an upper electrode deposited opposite the base electrode with the dielectric layers and the internal electrode being interposed therebetween; and a cover layer deposited on the upper electrode, has depositing an upper electrode layer which is to be the upper electrode, and a cover film which is to be the cover layer on the unsintered dielectric film which is to be the dielectric layer, to fabricate a lamination component, and sintering the lamination component.

Abstract: A thin film capacitor includes a metal foil, dielectric layers and internal electrode layers alternately disposed on the metal foil, and a top electrode layer on the topmost layer among the two or more dielectric layers. These layers have peripheries that define an outer profile flaring toward the metal foil as viewed from the stacking direction of the thin film capacitor, and at least one dielectric layer of two or more dielectric layers satisfies a relationship B>A>0 wherein A is a gap of the periphery of the internal electrode layer directly below the dielectric layer protruding from the periphery of the dielectric layer, and B is a gap of the periphery of the dielectric layer protruding from the periphery of the internal electrode layer or the top electrode layer directly above the dielectric layer. The thin film capacitor has a structure free from short-circuiting and reducing debris of broken dielectric material.

Abstract: In a dielectric element, the angle ? made by either the top face or the bottom face and the side faces is either 0°<?<89°, or is 91°<?<180°, and is an angle other than 89°???91°. By this means, the area of contact of the side faces of the dielectric element with a glass epoxy resin substrate and with insulating material is increased, adhesion with the resin substrates is improved, and strength and reliability can be enhanced when buried between the two resin substrates.

Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 ?mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23. are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 ?mRMS Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

Abstract: The present invention provides a wiring board including a metal plate that has a through hole formed so as to pass though both surfaces thereof by isotropic etching; an insulating layer that covers both surfaces of the metal plate and the inside surface of the through hole; a wiring layer formed on an upper surface of at least one surface of the insulating layer on; and a conductive via electrode formed in the through hole, wherein a diameter of the through hole is 100 ?m or less and a ratio of a thickness of the metal plate to the diameter of the through hole is 1 or more, preferably, 1.2 or more.

Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 ?mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 &mgr;mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23, are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 &mgr;mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

Abstract: A semiconductive ceramic composition capable of exhibiting excellent electrical and physical characteristics sufficient to be used for a boundary-layer type semiconductive ceramic capacitor and such a capacitor capable of being increased in dielectric constant and insulation resistance and exhibiting excellent solderability and tensile strength of electrodes. The composition includes a SrTiO.sub.3 base material and an additive for semiconductivity consisting of Y.sub.2 O.sub.3 and Nb.sub.2 O.sub.5. The Y.sub.2 O.sub.3 and Nb.sub.2 O.sub.5 each are present in an amount of 0.1 to 0.4 mol % based on the composition. The capacitor includes a semiconductive ceramic body formed of the composition, a first conductive layer formed on each of both surfaces of the body and a second conductive layer formed on the first conductive layer. A process for manufacturing the capacitor is also provided.

Abstract: A semiconductive ceramic composition capable of exhibiting excellent electrical and physical characteristics sufficient to be used for a boundary-layer type semiconductive ceramic capacitor and such a capacitor capable of being increased in dielectric constant and insulation resistance and exhibiting excellent solderability and tensile strength of electrodes. The composition includes a SrTiO.sub.3 base material and an additive for semiconductivity consisting of Y.sub.2 O.sub.3 and Nb.sub.2 O.sub.5. The Y.sub.2 O.sub.3 and Nb.sub.2 O.sub.5 each are present in an amount of 0.1 to 0.4 mol % based on the composition. The capacitor includes a semiconductive ceramic body formed of the composition, a first conductive layer formed on each of both surfaces of the body and a second conductive layer formed on the first conductive layer. A process for manufacturing the capacitor is also provided.

Abstract: A D-E hysteresis loop of ferroelectrics known in the art has a square shape when the ferroelectrics are a BaTiO.sub.3 single crystal. Such ferroelectrics are used as a non-linear dielectric element of, for example a pulse generating device. The non-linear dielectric element according to the present invention consists of a polycrystal, which is mainly composed of BaTiO.sub.3 and has the chemical composition expressed by the formula A.sub.y B.sub.z O.sub.3, wherein the molar ratio of y/z ranges from 0.92 to 0.99. The non-linearity is excellent and the temperature dependence of the A.sub.y B.sub.z O.sub.3 composition is considerably low.

Abstract: A D-E hysteresis loop of ferroelectrics known in the art has a square shape when the ferroelectrics are a BaTiO.sub.3 single crystal. Such ferroelectrics are used as a non-linear dielectric element of, for example a pulse generating device. The non-linear dielectric element according to the present invention consists of a polycrystal mainly composed of Ba(Ti.sub.0.90-0.98 Sn.sub.0.02-1.00)O.sub.3 and having an average grain diameter of from 10 to 60 .mu.m. The non-linearity is excellent and the temperature dependence of the non-linearity is considerably low.