Patents by Inventor Yasunobu Saito

Yasunobu Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240365831
    Abstract: A gel-like food which has a high protein content, is a uniform gel, and has swallowing properties of being easily ingestible by elderly people or people with difficulties in swallowing; and a method for producing the gel-like food. The gel-like food is produced by heating using thermal coagulation of proteins including 1-6 mass % of an egg white protein and 4-15 mass % of casein, the total protein content in the gel-like food being 5.5-25 mass %.
    Type: Application
    Filed: August 31, 2022
    Publication date: November 7, 2024
    Inventors: Soyoka TOKUNAGA, Yasunobu SAITO
  • Patent number: 12119396
    Abstract: According to one embodiment, a semiconductor device comprises a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer. Source and drain electrodes are on the second nitride semiconductor layer. A gate electrode is between the source electrode and the drain electrode. A third nitride semiconductor layer of p-type conductivity is on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: October 15, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yasunobu Saito
  • Publication number: 20240313045
    Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a third electrode, a second semiconductor layer, a third semiconductor layer, a fourth electrode, and a fourth semiconductor layer. The third semiconductor layer extends from the second semiconductor layer toward the first electrode side. A lower end of the third semiconductor layer at the first electrode side is positioned further toward the first electrode side than the lower surface of the second semiconductor layer and is separated from the insulating body. The third semiconductor layer is of the second conductivity type. The fourth electrode faces the second semiconductor layer via an other portion of the insulating body. The fourth semiconductor layer is located between the second semiconductor layer and the second electrode and electrically connected with the second electrode. The fourth semiconductor layer is of the first conductivity type.
    Type: Application
    Filed: August 15, 2023
    Publication date: September 19, 2024
    Inventors: Takuya YASUTAKE, Yasunobu SAITO, Tsuyoshi KACHI
  • Publication number: 20240096973
    Abstract: A semiconductor device includes: a first electrode; a semiconductor part located on the first electrode; a second electrode located in a first region on the semiconductor part; a third electrode located in a second region on the semiconductor part; an insulating member located in the semiconductor part in the first and second regions; a fourth electrode located in the insulating member in the first and second regions; a fifth electrode located in the insulating member between the first electrode and the fourth electrode in the first and second regions; and a conductive member located at least in the second region. The conductive member is connected to the third, fourth, and fifth electrodes.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 21, 2024
    Inventors: Keita SAITO, Kouta TOMITA, Tatsuya NISHIWAKI, Yasunobu SAITO
  • Publication number: 20230354859
    Abstract: The present invention addresses the problem of providing an oil-in-water emulsified seasoning in which deterioration of flavor over time is suppressed, and a method for producing the oil-in-water emulsified seasoning. The present invention is an oil-in-water emulsified seasoning containing 25-75 mass % of an oil and fat, 5-50 mass ppm of ?-carotene, and 1-5 mass ppm of lycopene, wherein the ?-carotene is contained in the oil and fat, and the lycopene is contained in a continuous phase. The present invention is also a method for producing an oil-in-water emulsified seasoning, the method involving emulsifying an oil phase that contains the oil and fat and the ?-carotene, and an aqueous phase that contains the lycopene.
    Type: Application
    Filed: September 22, 2021
    Publication date: November 9, 2023
    Applicant: The Nisshin OilliO Group, Ltd.
    Inventors: Hidetoshi Ishikawa, Yasunobu Saito
  • Publication number: 20220029006
    Abstract: According to one embodiment, a semiconductor device comprises a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer. Source and drain electrodes are on the second nitride semiconductor layer. A gate electrode is between the source electrode and the drain electrode. A third nitride semiconductor layer of p-type conductivity is on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventor: Yasunobu SAITO
  • Publication number: 20200229477
    Abstract: The present invention addresses the problem of providing a gel composition, which comprises a large amount of a fat or an oil containing medium-chain fatty acids in the constituting fatty acids thereof, shows no separation of the fat or oil and relieves gastric distress when eating, and a method for manufacturing the same. The gel composition according to the present invention, which is a gel composition prepared by gelling an oil-in-water type emulsion having an average emulsified particle size of 2-40 ?m, contains 20-60 mass % of triglycerides, wherein 40 mass % or more of the total constituting fatty acids of the triglycerides are medium-chain fatty acids.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Applicant: THE NISSHIN OILLIO GROUP, LTD.
    Inventors: Daisuke SUYAMA, Yasunobu SAITO
  • Publication number: 20200091330
    Abstract: According to one embodiment, a semiconductor device comprises a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer. Source and drain electrodes are on the second nitride semiconductor layer. A gate electrode is between the source electrode and the drain electrode. A third nitride semiconductor layer of p-type conductivity is on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode.
    Type: Application
    Filed: February 27, 2019
    Publication date: March 19, 2020
    Inventor: Yasunobu SAITO
  • Publication number: 20180103669
    Abstract: The present invention addresses the problem of providing a gel composition, which comprises a large amount of a fat or an oil containing medium-chain fatty acids in the constituting fatty acids thereof, shows no separation of the fat or oil and relieves gastric distress when eating, and a method for manufacturing the same. The gel composition according to the present invention, which is a gel composition prepared by gelling an oil-in-water type emulsion having an average emulsified particle size of 2-40 ?m, contains 20-60 mass % of triglycerides, wherein 40 mass % or more of the total constituting fatty acids of the triglycerides are medium-chain fatty acids. The triglycerides may comprise a medium-chain fatty acid triglyceride.
    Type: Application
    Filed: March 30, 2016
    Publication date: April 19, 2018
    Applicant: The Nisshin OilliO Group, Ltd.
    Inventors: Daisuke SUYAMA, Yasunobu SAITO
  • Publication number: 20180076311
    Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.
    Type: Application
    Filed: February 24, 2017
    Publication date: March 15, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu SAITO, Kohei OASA, Takuo KIKUCHI, Junji KATAOKA, Tatsuya SHIRAISHI, Akira YOSHIOKA, Kazuo SAKI
  • Patent number: 9917182
    Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Kohei Oasa, Takuo Kikuchi, Junji Kataoka, Tatsuya Shiraishi, Akira Yoshioka, Kazuo Saki
  • Publication number: 20170263716
    Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer on the first nitride semiconductor layer, a source electrode on the second nitride semiconductor layer and spaced from the source electrode, a drain electrode on the second nitride semiconductor layer and spaced from the source electrode, a gate electrode between the drain and source electrodes, an interlayer insulating film on the second nitride semiconductor layer, a first field plate electrode in contact with an upper surface of the second nitride semiconductor layer at a location between the gate and drain electrodes, and a second field plate electrode extending through the interlayer insulating film and connected to the first field plate electrode. An end of the second field plate electrode on the source electrode side is closer to the drain electrode than is an end of the first field plate electrode on the source electrode side.
    Type: Application
    Filed: August 22, 2016
    Publication date: September 14, 2017
    Inventors: Yasunobu SAITO, Toshiyuki NAKA
  • Patent number: 9698141
    Abstract: A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka
  • Publication number: 20170069623
    Abstract: A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 9, 2017
    Inventors: Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA
  • Publication number: 20170069747
    Abstract: A semiconductor device capable of suppressing current collapse is provided. The semiconductor device includes a substrate, a nitride semiconductor layer on the substrate, and including a first region and a second region having a thickness greater than that of the first region, a source electrode on the first region, a drain electrode on the second region, and a gate electrode on the first region between the source electrode and the drain electrode.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 9, 2017
    Inventors: Yasunobu SAITO, Toshiyuki NAKA, Nobuyuki SATO
  • Patent number: 9466705
    Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: October 11, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Toru Sugiyama, Yasunobu Saito, Kunio Tsuda
  • Patent number: 9412857
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito, Toru Sugiyama
  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Patent number: 9391142
    Abstract: A semiconductor device of this embodiment includes: a first semiconductor layer including AlXGa1-XN; a second semiconductor layer provided above the first semiconductor layer, and including undoped or n-type AlYGa1-YN; a first and second electrodes provided above the second semiconductor layer; a third semiconductor layer provided above the second semiconductor layer between the first electrode and the second electrode, is at a distance from each of the first and second electrodes, and including p-type AlZGa1-ZN; a control electrode provided above the third semiconductor layer; a fourth semiconductor layer provided above the third semiconductor layer between the first electrode and the control electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN; and a fifth semiconductor layer provided above a portion of the third semiconductor layer between the control electrode and the second electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Yasunobu Saito
  • Publication number: 20160079410
    Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI