Abstract: A semiconductor integrated circuit device includes: a serial signal input terminal that receives input of a command; a control signal input terminal that receives input of a control signal; and a circuit block that determines whether or not the circuit block has been selected using an identification code included in the command in the case where the control signal is activated, and if it is determined that the circuit block has been selected using the identification code, the circuit block performs an operation designated by the command.

Abstract: A drive circuit includes an output circuit having an output node that outputs, to a charge pump circuit, a drive clock signal for driving the charge pump circuit. The output circuit generates the drive clock signal based on a first clock signal and a second clock signal that is a signal whose voltage level does not change in a period during which the voltage level of the first clock signal changes, and controls, based on the second clock signal, an impedance of the output node so as to be up, in a period before the voltage levels of the drive clock signal changes.

Abstract: A latch circuit that latches stored data of a nonvolatile storage device used for setting the function of a semiconductor device and adjusting the characteristics of the semiconductor device required a dedicated input-output circuit for a test of the semiconductor device. By providing a dummy storage device, it becomes possible to perform a test of the semiconductor device without providing a dedicated input-output circuit.

Abstract: A drive circuit includes an output circuit having an output node that outputs, to a charge pump circuit, a drive clock signal for driving the charge pump circuit. The output circuit generates the drive clock signal based on a first clock signal and a second clock signal that is a signal whose voltage level does not change in a period during which the voltage level of the first clock signal changes, and controls, based on the second clock signal, an impedance of the output node so as to be up, in a period before the voltage levels of the drive clock signal changes.

Abstract: A latch circuit that latches stored data of a nonvolatile storage device used for setting the function of a semiconductor device and adjusting the characteristics of the semiconductor device required a dedicated input-output circuit for a test of the semiconductor device. By providing a dummy storage device, it becomes possible to perform a test of the semiconductor device without providing a dedicated input-output circuit.

Abstract: An output circuit which outputs a data signal from an output terminal after setting the output terminal to a potential intermediate between a power supply line potential and a ground line potential. The output circuit includes an output drive configured of first and second transistors. The first transistor has a first control terminal to which is input a first control signal. The second transistor has a second control terminal to which is input a second control signal. It further includes a setting member which controls the first and second control signals to set the first and second transistors to the off state. It further includes a shorting member which shorts one of the first and second control terminals and the output terminal. Moreover, before the data signal is output, the transistors are set to the off state by the setting member, after which shorting is carried out according to the potential of the output terminal, and the output terminal is set to an intermediate potential.

Abstract: A semiconductor memory device that steps up word lines, each of whose length is short enough to stay within one of the blocks that is formed by dividing a memory cell array into multiple blocks. The device includes multiple memory cells connected to pairs of bit lines and word lines at intersections of the pairs of bit lines and the word lines. Multiple memory cell array blocks are formed by dividing the region where the memory cells are arranged into blocks. A first step-up line is commonly used in stepping-up the word lines. A step-up circuit is constructed of a step-up capacitor, which is connected to the first step-up line and a switching transistor, which precharges the step-up capacitor. The semiconductor memory device also has a step-up control circuit that outputs a precharge control signal, which precharges the step-up capacitor by ON driving the switching transistor, and a step-up driving signal, which changes the potential of the negative terminal of the step-up capacitor of the step-up circuit.

Abstract: A first word line connects the gate electrodes of first transfer transistors in adjacent memory cells. A second word line connects the gate electrodes of second transfer transistors in adjacent memory cells. A ground line connects the source regions of first and second driver transistors. The first and second word lines and ground line are formed by a wiring layer different from the wiring layer that forms the gate electrodes of the first and second transfer transistors. The ground line shields the first and second driver transistors, TFTs and the like. Drain contacts include chamfered sides between which the ground line is disposed.

Abstract: A noise resistant static memory device is presented which is capable of reading correct data from the memory cells even in the presence of a sharp pulse noise. This is achieved by providing a signal change detection circuit which detects that a extraneous signal having a very short pulse width has been included in the read out data. In the conventional design based on auto power-down system, this type of sharp pulse will result in the destruction of the latched data because of automatic resetting of the memory read out circuit. In the invented device, resetting is nullified simultaneously with the detection of the noise signal, thereby enabling the data read out circuit to read the data again, thereby enabling to repeat the reading step. The device thus provides noise-resistant reliable memory read out performance.

Abstract: A semiconductor memory adapted to receive a chip selection signal and address signal, composed of: a signal generating circuit for generating inner selection signals with respect to the chip selection signal, a pulse generating circuit for detecting any changes in the address signals and generating a pulse signal; and a pulse width changing circuit for inputting the pulse signal to output a control signal for precharging or equalizing the data lines of a memory cell array. The pulse width changing circuit outputs the control signal having a pulse whose pulse width corresponds to what is obtained by converting the pulse width of the pulse signal into a longer one when the inner selection signals are in the chip-selecting condition.