Patents by Inventor Yasunobu Yanagisawa

Yasunobu Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9858954
    Abstract: A test fixture for testing a slider configured for heat assisted magnetic recording. The test fixture has a three dimensional structure with contact pads configured to make contact with electrically conductive contact pads at the trailing edge of the slider. The test fixture also has a structure with a contact pad configured to make electrical contact with a contact pad formed at a backside surface of the slider.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 2, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Noriyuki Saiki, Kazue Kudo, Takaharu Niimi, Yasunobu Yanagisawa
  • Patent number: 7177121
    Abstract: In a magnetoresistive head according to the present invention, a magnetic domain control film formed at the end of a free layer of a stack of magnetoresistive layers is formed of a Co alloy film, and an underlayer controlling the crystallization state of the Co alloy film and an amorphous metal film layer for controlling the crystallization state of the underlayer are disposed below the magnetic domain control film.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: February 13, 2007
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Shuichi Kojima, Norihiro Ookawa, Koji Okazaki, Yasunobu Yanagisawa, Akira Morinaga
  • Patent number: 6864549
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Publication number: 20040145836
    Abstract: In a magnetoresistive head according to the present invention, a magnetic domain control film formed at the end of a free layer of a stack of magnetoresistive layers is formed of a Co alloy film, and an underlayer controlling the crystallization state of the Co alloy film and an amorphous metal film layer for controlling the crystallization state of the underlayer are disposed below the magnetic domain control film.
    Type: Application
    Filed: September 16, 2003
    Publication date: July 29, 2004
    Applicant: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Shuichi Kojima, Norihiro Ookawa, Koji Okazaki, Yasunobu Yanagisawa, Akira Morinaga
  • Publication number: 20040036139
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.
    Type: Application
    Filed: August 27, 2003
    Publication date: February 26, 2004
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Patent number: 6661062
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Publication number: 20030189799
    Abstract: A magnetoresistive reproducing head is manufactured by forming a magnetoresistive film and a lead layer continuously, then etching only the lead layer by using a first layer photo-resist pattern, forming a second layer photo-resistive pattern while leaving the first layer photo-resist pattern, etching the magnetoresistive film and then forming a domain control film and an outer lead layer, thereby enabling to avoid the effect at all on the positional relation between the lead layer and domain control film, whereby a head in which the riding amount of the lead layer on the magnetoresistive film is in right-to-left symmetry and the sensitivity profile is in right-to-left symmetry can be manufactured at a good yield.
    Type: Application
    Filed: August 16, 2002
    Publication date: October 9, 2003
    Inventors: Yasunobu Yanagisawa, Akira Morinaga, Masatoshi Arasawa, Shuichi Kojima, Makoto Morijiri
  • Publication number: 20030137014
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.
    Type: Application
    Filed: February 5, 2003
    Publication date: July 24, 2003
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Patent number: 6538293
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: March 25, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Publication number: 20020130342
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.
    Type: Application
    Filed: May 10, 2002
    Publication date: September 19, 2002
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Patent number: 6433398
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: August 13, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Patent number: 6423588
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the may reliably operate even at a low power-supply voltage.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: July 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka