Patents by Inventor Yasunobu Yoshizaki

Yasunobu Yoshizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240056040
    Abstract: A radio-frequency module includes a power amplifier, a first bias circuit connected to the power amplifier, and a second bias circuit connected to the power amplifier. The first bias circuit includes a register that receives a first digital control signal corresponding to a power mode of the power amplifier and a current generation circuit that generates, based on information in the register, a first bias current, and the second bias circuit includes another register that receives a second digital control signal corresponding to the power mode and a current generation circuit that generates, based on information in the other register, a second bias current.
    Type: Application
    Filed: June 1, 2023
    Publication date: February 15, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi SAKURAI, Toshiki MATSUI, Yasunobu YOSHIZAKI, Fuminori MORISAWA
  • Patent number: 10348253
    Abstract: A radio-frequency module includes a substrate, a low-noise amplifier circuit being a first amplifier circuit arranged in a first area in the substrate, a power amplifier circuit being a second amplifier circuit arranged in a second area in the substrate, and a duplexer being a component arranged between the first area and the second area in the substrate and having a heat generating property lower than that of the power amplifier circuit. The low-noise amplifier circuit includes a bias circuit configured to generate a bias current dependent on temperature characteristics of a first diode, a voltage generating circuit configured to generate a voltage dependent on temperature characteristics of a second diode as an operating voltage for the bias circuit, and an amplifier circuit configured to operate at an operating point determined by the bias current.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasunobu Yoshizaki
  • Publication number: 20180159482
    Abstract: A radio-frequency module includes a substrate, a low-noise amplifier circuit being a first amplifier circuit arranged in a first area in the substrate, a power amplifier circuit being a second amplifier circuit arranged in a second area in the substrate, and a duplexer being a component arranged between the first area and the second area in the substrate and having a heat generating property lower than that of the power amplifier circuit. The low-noise amplifier circuit includes a bias circuit configured to generate a bias current dependent on temperature characteristics of a first diode, a voltage generating circuit configured to generate a voltage dependent on temperature characteristics of a second diode as an operating voltage for the bias circuit, and an amplifier circuit configured to operate at an operating point determined by the bias current.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 7, 2018
    Inventor: Yasunobu Yoshizaki
  • Patent number: 9344044
    Abstract: The present invention provides a power amplifier that can reduce irregularities in characteristics such as gains. A high-frequency power amplifier that is used for a mobile communication terminal includes: an amplifier element that includes a composite semiconductor bipolar transistor and that amplifies high-frequency power of a predetermined frequency band with a bias voltage and a bias current supplied thereto; a bias circuit that supplies the bias voltage and the bias current to the amplifier element on the basis of a bias reference voltage; a bias reference voltage supply circuit that generates and supplies the bias reference voltage to the bias circuit; and a bias reference voltage control unit that controls the bias reference voltage supply circuit so as to generate the bias reference voltage of a voltage corresponding to a given signal.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 17, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasunobu Yoshizaki
  • Publication number: 20150054587
    Abstract: The present invention provides a power amplifier that can reduce irregularities in characteristics such as gains. A high-frequency power amplifier that is used for a mobile communication terminal includes: an amplifier element that includes a composite semiconductor bipolar transistor and that amplifies high-frequency power of a predetermined frequency band with a bias voltage and a bias current supplied thereto; a bias circuit that supplies the bias voltage and the bias current to the amplifier element on the basis of a bias reference voltage; a bias reference voltage supply circuit that generates and supplies the bias reference voltage to the bias circuit; and a bias reference voltage control unit that controls the bias reference voltage supply circuit so as to generate the bias reference voltage of a voltage corresponding to a given signal.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 26, 2015
    Inventor: Yasunobu Yoshizaki
  • Patent number: 8810285
    Abstract: In a semiconductor integrated circuit apparatus and a radio-frequency power amplifier module, a log detection portion including multiple-stage amplifier circuits, multiple level detection circuits, adder circuits, and a linear detection portion including a level detection circuit are provided. Output current from the log detection portion and output current from the linear detection portion are multiplied by different coefficients and the results of the multiplication are added to each other to realize the multiple detection methods. For example, current resulting from multiplication of the output current from the log detection portion by ×6/5 is added to the output current from the linear detection portion to realize a log detection method and, current resulting from multiplication of the output current from the log detection portion by ×? is added to current resulting from multiplication of the output current from the linear detection portion by ×3 to realize a log-linear detection method.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 19, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke Shimamune, Yasunobu Yoshizaki, Norio Hayashi, Takayuki Tsutsui
  • Publication number: 20140015568
    Abstract: In a semiconductor integrated circuit apparatus and a radio-frequency power amplifier module, a log detection portion including multiple-stage amplifier circuits, multiple level detection circuits, adder circuits, and a linear detection portion including a level detection circuit are provided. Output current from the log detection portion and output current from the linear detection portion are multiplied by different coefficients and the results of the multiplication are added to each other to realize the multiple detection methods. For example, current resulting from multiplication of the output current from the log detection portion by ×6/5 is added to the output current from the linear detection portion to realize a log detection method and, current resulting from multiplication of the output current from the log detection portion by ×1/5 is added to current resulting from multiplication of the output current from the linear detection portion by ×3 to realize a log-linear detection method.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke SHIMAMUNE, Yasunobu YOSHIZAKI, Norio HAYASHI, Takayuki TSUTSUI
  • Patent number: 8385875
    Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasunobu Yoshizaki, Tetsuya Wakuda
  • Publication number: 20090143043
    Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.
    Type: Application
    Filed: February 4, 2009
    Publication date: June 4, 2009
    Inventors: Yasunobu YOSHIZAKI, Tetsuya WAKUDA
  • Patent number: 7493098
    Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: February 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasunobu Yoshizaki, Tetsuya Wakuda
  • Publication number: 20060223474
    Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.
    Type: Application
    Filed: March 24, 2006
    Publication date: October 5, 2006
    Inventors: Yasunobu Yoshizaki, Tetsuya Wakuda