Abstract: A Reed-Solomon coding decoder for use in error correction has a plurality of processing elements (PEs) each including a selector having a plurality of inputs and at least one output, a multiplier which receives as at least one of the inputs thereof the output from the selector, an adder for adding the outputs of the multiplier, and m-stages of registers for storing the outputs of the adder and the selector. The PEs are connected in a predetermined pattern to realize a compact construction of a Reed-Solomon code decoder.

Abstract: There is a signal processing apparatus for use in the error correction field for correcting errors in systems such as Reed Solomon code. This apparatus has three kinds of cells which execute the proceses in the decoding of the BCH code: namely, a syndrome cell to produce syndromes; a GCD (greatest common divisor) cell to produce an error position polynomial and an error evaluation polynomial; and an evaluation cell to estimate and correct errors in position and size. The required cells are one-dimensionally arranged in accordance with the error correcting capability of the code which is used. The algorithm for the signal processes in the conventional communication line is modified to the algorithm suitable for parallel processing. The signal processes can be executed using parallel processors due to the pipeline processes. Those dedicated cells can be realized by the hardwares, respectively.