Abstract: A bandgap circuit according to an embodiment of the present invention includes a load circuit arranged between an output terminal and a first power supply line, an output transistor arranged between the output terminal and a second power supply line, and outputs a desired reference voltage in accordance with control voltage, a control voltage generating circuit generating the control voltage applied to the output transistor, and a filter arranged between the output transistor and the control voltage generating circuit.

Abstract: A data processing apparatus has a main memory and a plurality of memory banks. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary memory space in the main memory. A main return instruction designating a particular main address of the main memory is stored in the memory address represented by a particular bank address of the nth memory bank. When the bank switching instruction is read, the readout destination is branched to the first memory bank. Data stored in the first memory bank, the second memory bank, . . . , and the nth memory bank are successively read. When the main return instruction is read from the nth memory bank, the readout destination returns to the main memory.

Abstract: A data processing apparatus has a main memory having a plurality of successive memory spaces with a series of main addresses assigned thereto and a plurality of memory banks having a plurality of successive memory spaces with a series of bank addresses assigned commonly thereto. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary memory space in the main memory. First through (n-1)th memory banks each have a virtual space where no stored data is present in respective final bank address thereof. A main return instruction designating a particular main address of the main memory is stored in the memory address represented by a particular bank address of the nth memory bank. Stored data in the main memory is read successively from the main addresses beginning with a head address. When the bank switching instruction is read, the readout destination is branched to the first memory bank. Data stored in the first memory bank, the second memory bank, .