Patents by Inventor Yasunori Fukumitsu

Yasunori Fukumitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220033209
    Abstract: An image reading device includes: a transport unit configured to transport a medium; an emission unit configured to emit an ultrasonic wave in accordance with a driving voltage and a reception unit configured to receive the ultrasonic wave, the emission unit and the reception unit being disposed so that a transport path for the medium transported by the transport unit is interposed therebetween; a reading unit configured to read the medium; and a control unit configured to detect presence or absence of multi-feed of the medium on the basis of a signal received by the reception unit. The image reading device is configured to switch a posture into any of a first posture or a second posture. The first posture is a posture in which the transport path is sloped relative to a mounting surface. The second posture is a posture in which an angle of the transport path relative to the mounting surface is smaller than that in the first posture.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 3, 2022
    Inventor: Yasunori FUKUMITSU
  • Patent number: 11212402
    Abstract: A medium transporting apparatus includes a feeding roller that rotates to transport a medium along a transportation path, an electrode installed downstream of the feeding roller on the transportation path and having conductivity, and an electric charge detecting circuit that outputs a signal having a magnitude corresponding to an amount of an electric charge, which moves from the medium to the electrode after the medium being transported along the transportation path comes into contact with the electrode.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: December 28, 2021
    Assignee: Seiko Epson Corporation
    Inventors: Yusuke Fukasawa, Hidetoshi Masuda, Yasunori Fukumitsu
  • Publication number: 20210067644
    Abstract: A medium transporting apparatus includes a feeding roller that rotates to transport a medium along a transportation path, an electrode installed downstream of the feeding roller on the transportation path and having conductivity, and an electric charge detecting circuit that outputs a signal having a magnitude corresponding to an amount of an electric charge, which moves from the medium to the electrode after the medium being transported along the transportation path comes into contact with the electrode.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 4, 2021
    Inventors: Yusuke FUKASAWA, Hidetoshi MASUDA, Yasunori FUKUMITSU
  • Patent number: 10432809
    Abstract: A clipping processor is configured to estimate a background pixel value which is a read value of a background board and to clip an image of an original document from a read image based on the background pixel value which is estimated, the read value changing due to an increase in distance between a sensor and the background board caused by the original document, the read image being a result of reading an area including the original document and the background board.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 1, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Yasunori Fukumitsu
  • Publication number: 20180343353
    Abstract: A clipping processor is configured to estimate a background pixel value which is a read value of a background board and to clip an image of an original document from a read image based on the background pixel value which is estimated, the read value changing due to an increase in distance between a sensor and the background board caused by the original document, the read image being a result of reading an area including the original document and the background board.
    Type: Application
    Filed: April 20, 2018
    Publication date: November 29, 2018
    Inventor: Yasunori FUKUMITSU
  • Patent number: 7458652
    Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: December 2, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
  • Patent number: 7188197
    Abstract: A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by a word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: March 6, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Yasunori Fukumitsu, Masahiro Kimura
  • Patent number: 7177955
    Abstract: Record controlling data received by an interface unit is transferred to a change controlling block, and transferred to a head analyzing block so that analysis of its head can be performed. In case the data following the head is a command, it is stored in a command storing register, and in case of compressed recording data, it is transferred to a data transfer controlling block. A MPU accesses the command storing register to analyze the command. The compressed recording data is stored in a FIFO memory via a first dedicated bus from the data transfer controlling block, and transferred to a DECU via a second dedicated bus.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Yasunori Fukumitsu, Masahiro Kimura
  • Patent number: 7167932
    Abstract: Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: January 23, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
  • Patent number: 7167933
    Abstract: A data transferring apparatus has an ASIC (Application Specific Integrated Circuit), and the ASIC incorporates an interface unit, a head controlling unit, a receiving buffer unit and a DECU, which are coupled to be capable of transferring data. The DECU incorporates a development processing controller having a decode circuit for performing hardware development on compressed recording data, and a line buffer storing developed recording data. The DECU and the head controlling unit are coupled by an internal bus IB in order to perform data transfer.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: January 23, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Kimura, Yasunori Fukumitsu
  • Publication number: 20060187248
    Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.
    Type: Application
    Filed: April 19, 2006
    Publication date: August 24, 2006
    Applicant: Seiko Epson Corporation
    Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
  • Patent number: 7083244
    Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: August 1, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
  • Publication number: 20050038929
    Abstract: A data transferring apparatus for transferring liquid ejection data, has a decode unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit, wherein the line buffer comprises two faces of buffer areas in order to store the developed data, the developed liquid ejection data is sequentially stored in a first face of the buffer areas, while the developed liquid ejection data is sequentially stored in a second face of the buffer areas when the developed data of predetermined words has been accumulated, and the developed liquid ejection data is stored in a first face one word each, while the liquid ejection data already developed in a second face is simultaneously transferred to an external memory one word each.
    Type: Application
    Filed: October 22, 2003
    Publication date: February 17, 2005
    Inventors: Yasunori Fukumitsu, Masahiro Kimura
  • Publication number: 20050001862
    Abstract: A data transferring apparatus has an ASIC (Application Specific Integrated Circuit), and the ASIC incorporates an interface unit, a head controlling unit, a receiving buffer unit and a DECU, which are coupled to be capable of transferring data. The DECU incorporates a development processing controller having a decode circuit for performing hardware development on compressed recording data, and a line buffer storing developed recording data. The DECU and the head controlling unit are coupled by an internal bus IB in order to perform data transfer.
    Type: Application
    Filed: August 26, 2003
    Publication date: January 6, 2005
    Inventors: Masahiro Kimura, Yasunori Fukumitsu
  • Publication number: 20040255060
    Abstract: Record controlling data received by an interface unit is transferred to a change controlling block, and transferred to a head analyzing block so that analysis of its head can be performed. In case the data following the head is a command, it is stored in a command storing register, and in case of compressed recording data, it is transferred to a data transfer controlling block. A MPU accesses the command storing register to analyze the command. The compressed recording data is stored in a FIFO memory via a first dedicated bus from the data transfer controlling block, and transferred to a DECU via a second dedicated bus.
    Type: Application
    Filed: August 26, 2003
    Publication date: December 16, 2004
    Inventors: Yasunori Fukumitsu, Masahiro Kimura
  • Publication number: 20040143611
    Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.
    Type: Application
    Filed: August 26, 2003
    Publication date: July 22, 2004
    Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
  • Publication number: 20040083313
    Abstract: Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.
    Type: Application
    Filed: August 26, 2003
    Publication date: April 29, 2004
    Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
  • Patent number: 4657805
    Abstract: In a dust cover for photomask reticle purposes which consists essentially of a supporting frame and a thin film bonded to a surface of the frame, the dust cover is improved in transparency by constructing at least the outermost layers of the thin film with thin films of a fluoropolymer which exhibits an average transmittance of at least 90% for rays of wavelengths from 240 to 290 nm and an average transmittance of at least 93.5% for rays of wavelengths from 290 to 500 nm, when having a thickness of 10 .mu.m, and has a refractive index of up to 1.42.
    Type: Grant
    Filed: June 13, 1985
    Date of Patent: April 14, 1987
    Assignee: Asahi Kasei Kogyo Kabushiki Kaisha
    Inventors: Yasunori Fukumitsu, Mitsuo Kohno