Abstract: An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address and data buses to peripheral blocks. There is also provided a clock supply unit to supply clock signals in which at least one of the clock signals has a phase different from those of the remaining clock signals and the clock signals do not accomplish the setting operation at the same time.

Abstract: A semiconductor integrated circuit has a self-oscillation circuit 5 for generating an internal clock signal ICK, a frequency division circuit 6 for generating a divided clock signal DCK based on an external clock signal CK, a switching circuit 7 connected to the self-oscillation circuit 5 and a frequency division circuit 6 and selectively outputting one of the internally clock signal ICK and the divided clock signal DCK in response to a control signal STBY, a controller 3 connected to the self-oscillation circuit 5 and the frequency division circuit 6 and the switching circuit 7, receiving a mode signal, and outputting the control signal STBY in accordance with the mode signal, when the mode signal is in a standby mode state, the self-oscillation circuit 5 is stopped and the switching circuit 7 selects the divided clock signal DCK, when the mode signal is in a normal operating state, the switching circuit 7 selects the internally clock signal ICK, and a charge pump circuit 8 receiving one of the internal cloc

Abstract: A data processor is disclosed which shows an improved real time performance by carrying out the starting and clearing operations of a timer in response to an external trigger input. In the timer unit of the unit of the data processor, a flip-flop is set during the low level period of a count enable signal, and a prescaler and a timer are cleared and inactivated by bringing the outputs of OR gates to the-high level. As the count-enable signal goes to the high level, an edge-detection circuit output a detection pulse by detecting a level change of the external trigger signal. The flip-flop is reset by the detection pulse, and the operation of the prescaler is started and a count clock is supplied to the timer to start the counting operation of the timer.

Abstract: A clock signal generation circuit is disclosed which receives a reference clock and detects, in response thereto, the loss of the reference clock. A phase comparator 13, detects the phase difference between the reference clock signal and an stabilized clock from a PLL synthesizer, a signal DOWNB state of the phase comparator 13 is fixed to "0" level at the time of loss of the reference clock signal where the reference clock can be fixed to "0" or "1" level. The signal DOWNB is monitored using a reference clock loss detection circuit 12. If the signal DOWNB stays at the "0" level for a prescribed length of time, the reference clock loss detection circuit 12 judges that the reference clock is lost and brings an XTALFAIL signal to the active state.

Abstract: A pulse generator includes an event counter receiving an external clock for counting the external clock, a first compare register coupled to the event counter for generating a first equal signal when a count value of the event counter becomes equal to a value set in the first compare register. The first equal signal is supplied to the event counter so as to clear the event counter. A free-running counter receives an internal clock for counting the internal clock, and a second compare register is coupled to the free-running counter for generating a second equal signal when a count value of the free-running counter becomes equal to a value set in the second compare register.